From 3b2d5c3a0a63b17d41c5c29887a21b1a6bd0cb6c Mon Sep 17 00:00:00 2001 From: jf Date: Wed, 4 Nov 2026 06:31:20 +0000 Subject: [PATCH] =?UTF-8?q?=E5=88=A0=E9=99=A4=E7=9B=AE=E5=BD=95=E3=80=8CHD?= =?UTF-8?q?MI=E3=80=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- HDMI/LT8912B-HDMI-extra.patch | 301 -- HDMI/LT8912B-HDMI.patch | 3596 ----------------- HDMI/LT8912B/LT8912B Ap note.pdf | Bin 1320884 -> 0 bytes HDMI/LT8912B/LT8912B PCB layout 建议.txt | 5 - HDMI/LT8912B/LT8912B 差分走线参考.png | Bin 637961 -> 0 bytes HDMI/LT8912B/LT8912B 输入MIPI 信号的要求.pdf | Bin 180556 -> 0 bytes HDMI/LT8912B/LT8912B_Datasheet_R1.2(1).pdf | Bin 6278593 -> 0 bytes HDMI/LT8912B/LT8912B_Linux_Driver_v1.0.zip | 3 - .../LT8912B/LT8912B_Linux_Driver_v1.0/Kconfig | 9 - .../LT8912B_Linux_Driver_v1.0/Makefile | 5 - ...river Introduction document (English).docx | Bin 1185583 -> 0 bytes .../LT8912B_Linux_Driver_v1.0/doc/Makefile | 27 - .../include/LT8912B.h | 72 - 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b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi ---- a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -42,9 +42,9 @@ - hfront-porch = <88>; - hsync-len = <44>; - hback-porch = <148>; -- vfront-porch = <56>; -- vsync-len = <6>; -- vback-porch = <60>; -+ vfront-porch = <4>; -+ vsync-len = <5>; -+ vback-porch = <36>; - }; - }; - }; -diff --git a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi ---- a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -42,9 +42,9 @@ - hfront-porch = <88>; - hsync-len = <44>; - hback-porch = <148>; -- vfront-porch = <56>; -- vsync-len = <6>; -- vback-porch = <60>; -+ vfront-porch = <4>; -+ vsync-len = <5>; -+ vback-porch = <36>; - }; - }; - }; -diff --git a/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi ---- a/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -47,9 +47,9 @@ - hfront-porch = <88>; - hsync-len = <44>; - hback-porch = <148>; -- vfront-porch = <56>; -+ vfront-porch = <38>; - vsync-len = <6>; -- vback-porch = <60>; -+ vback-porch = <40>; - }; - }; - }; -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c -@@ -9,6 +9,7 @@ - u8 Hsync_L, Hsync_H, Vsync_L, Vsync_H; - u8 mipi_det_fail_count = 0; - u8 mipi_relock_count = 0; -+bool mipi_video_ready = 0; - - - bool suspend_on = 0; -@@ -24,11 +25,13 @@ - struct video_timing video_1280x720_60Hz = {110, 40, 220, 1280, 1650, 5, 5, 20, 720, 750, 1,1, 4, AR_16_9, 74250}; - struct video_timing video_1280x800_60Hz = {28, 32, 100, 1280, 1440, 2, 6, 15, 800, 823, 0,0, 0, AR_16_9, 71000}; - //struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 4, 5, 36, 1080, 1125, 1,1,16, AR_16_9, 148500}; --struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 56, 6, 60, 1080, 1202, 1,1, 0, AR_16_9, 153600}; -+struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 4, 5, 36, 1080, 1125, 1,1,16, AR_16_9, 153600}; - - struct video_timing *video; - --void DDSConfig(void); -+void DDSConfig(struct video_timing *video_format); -+void HdmiOutput(bool on); -+u8 LT8912_Get_HPD(void); - - void DigitalClockEn(void) - { -@@ -72,25 +75,66 @@ - { - u8 VIC = video_format->vic; - u8 AR = video_format->aspact_ratio; -- u8 pb0,pb2,pb4,Sync_Polarity; -+ u8 pb0,pb1,pb2,pb4,Sync_Polarity; -+ u8 pb6, pb7, pb8, pb9, pb10, pb11, pb12, pb13; -+ u8 checksum; - - I2CADR = 0x94; - HDMI_WriteI2C_Byte(0x3c,0x41); //enable null package - - Sync_Polarity = (video_format->h_polarity*0x02) + (video_format->v_polarity*0x01); -- pb2 = (AR<<4) + 0x08; -- pb4 = VIC; -- pb0 = (((pb2 + pb4) <= 0x5f)?(0x5f - pb2 - pb4):(0x15f - pb2 - pb4)); -+ if (video_format->hact == 1920 && video_format->vact == 1080) { -+ Sync_Polarity = 0x03; -+ pb1 = 0x1c; -+ pb2 = 0xa8; -+ pb4 = 0x10; -+ pb6 = 0x29; -+ pb7 = 0x00; -+ pb8 = 0x61; -+ pb9 = 0x04; -+ pb10 = 0xc0; -+ pb11 = 0x00; -+ pb12 = 0x40; -+ pb13 = 0x08; -+ } else { -+ pb1 = 0x10; -+ pb2 = (AR<<4) + 0x08; -+ pb4 = VIC; -+ pb6 = 0x00; -+ pb7 = 0x00; -+ pb8 = 0x00; -+ pb9 = 0x00; -+ pb10 = 0x00; -+ pb11 = 0x00; -+ pb12 = 0x00; -+ pb13 = 0x00; -+ } -+ -+ checksum = 0x82 + 0x02 + 0x0d + pb1 + pb2 + pb4; -+ checksum += pb6 + pb7 + pb8 + pb9; -+ checksum += pb10 + pb11 + pb12 + pb13; -+ pb0 = 0x100 - checksum; - - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0xab,Sync_Polarity); //sync polarity - - I2CADR = 0x94; - HDMI_WriteI2C_Byte(0x43,pb0); //PB0:check sum -- HDMI_WriteI2C_Byte(0x44,0x10); //PB1:RGB888 -+ HDMI_WriteI2C_Byte(0x44,pb1); //PB1 - HDMI_WriteI2C_Byte(0x45,pb2); //PB2 - HDMI_WriteI2C_Byte(0x46,0x00); //PB3 - HDMI_WriteI2C_Byte(0x47,pb4); //PB4:vic -+ HDMI_WriteI2C_Byte(0x49,pb6); -+ HDMI_WriteI2C_Byte(0x4a,pb7); -+ HDMI_WriteI2C_Byte(0x4b,pb8); -+ HDMI_WriteI2C_Byte(0x4c,pb9); -+ HDMI_WriteI2C_Byte(0x4d,pb10); -+ HDMI_WriteI2C_Byte(0x4e,pb11); -+ HDMI_WriteI2C_Byte(0x4f,pb12); -+ HDMI_WriteI2C_Byte(0x50,pb13); -+ printk("%s AviInfoframe %ux%u pb0=0x%02x pb1=0x%02x pb2=0x%02x vic=%u sync=0x%02x\n", -+ LOG_FLAG, video_format->hact, video_format->vact, -+ pb0, pb1, pb2, pb4, Sync_Polarity); - } - - void MipiAnalog(void) -@@ -128,7 +172,13 @@ - - void MIPI_Video_Setup(struct video_timing *video_format) - { -+ u8 settle = 0x10; -+ -+ if (video_format->vact == 1080) -+ settle = 0x0a; -+ - I2CADR = 0x92; -+ HDMI_WriteI2C_Byte(0x11, settle); // settle - HDMI_WriteI2C_Byte(0x18,(u8)(video_format->hs%256)); // hwidth - HDMI_WriteI2C_Byte(0x19,(u8)(video_format->vs%256)); // vwidth - HDMI_WriteI2C_Byte(0x1c,(u8)(video_format->hact%256)); // H_active[7:0] -@@ -146,6 +196,10 @@ - HDMI_WriteI2C_Byte(0x3d,(u8)(video_format->hbp/256)); // HBP[15:8] - HDMI_WriteI2C_Byte(0x3e,(u8)(video_format->hfp%256)); // HFP[7:0] - HDMI_WriteI2C_Byte(0x3f,(u8)(video_format->hfp/256)); // HFP[15:8] -+ printk("%s MIPI_Video_Setup %ux%u total=%ux%u pclk=%u settle=0x%02x vic=%u\n", -+ LOG_FLAG, video_format->hact, video_format->vact, -+ video_format->htotal, video_format->vtotal, -+ video_format->pclk_khz, settle, video_format->vic); - video = video_format; - } - -@@ -168,19 +222,26 @@ - - MipiAnalog(); - MipiBasicSet(); -- DDSConfig(); -+ DDSConfig(&video_1920x1080_60Hz); - MIPI_Video_Setup(&video_1920x1080_60Hz); - AviInfoframe(&video_1920x1080_60Hz); - MIPIRxLogicRes(); - } - --void DDSConfig(void) -+void DDSConfig(struct video_timing *video_format) - { -+ u32 dds_word; -+ -+ dds_word = (video_format->pclk_khz / 1000) * 0x16C16; -+ dds_word += ((video_format->pclk_khz % 1000) * 0x16C16 + 500) / 1000; -+ - I2CADR = 0x92; -- HDMI_WriteI2C_Byte(0x4e,0x93);//strm_sw_freq_word[ 7: 0] -- HDMI_WriteI2C_Byte(0x4f,0x3E);//strm_sw_freq_word[15: 8] -- HDMI_WriteI2C_Byte(0x50,0x29);//strm_sw_freq_word[23:16] -+ HDMI_WriteI2C_Byte(0x4e,(u8)(dds_word & 0xff));//strm_sw_freq_word[ 7: 0] -+ HDMI_WriteI2C_Byte(0x4f,(u8)((dds_word >> 8) & 0xff));//strm_sw_freq_word[15: 8] -+ HDMI_WriteI2C_Byte(0x50,(u8)((dds_word >> 16) & 0xff));//strm_sw_freq_word[23:16] - HDMI_WriteI2C_Byte(0x51,0x80);//[0]=strm_sw_freq_word[24] -+ printk("%s DDSConfig pclk=%u kHz word=0x%06x\n", -+ LOG_FLAG, video_format->pclk_khz, dds_word); - HDMI_WriteI2C_Byte(0x1e,0x4f); - HDMI_WriteI2C_Byte(0x1f,0x5e);//full_value 464 - HDMI_WriteI2C_Byte(0x20,0x01); -@@ -231,8 +292,15 @@ - I2CADR = 0x94; - HDMI_WriteI2C_Byte(0x06,0x08); - HDMI_WriteI2C_Byte(0x07,0xF0); -- HDMI_WriteI2C_Byte(0x34,0xD2);//0xE2:32FS; 0xD2:64FS -+ HDMI_WriteI2C_Byte(0x09,0x00); -+ HDMI_WriteI2C_Byte(0x34,0xE2);//0xE2:32FS; 0xD2:64FS -+ HDMI_WriteI2C_Byte(0x35,0x00);//N = 6144(0x1800) -+ HDMI_WriteI2C_Byte(0x36,0x18); -+ HDMI_WriteI2C_Byte(0x37,0x00); -+ HDMI_WriteI2C_Byte(0x3c,0x41); -+ HDMI_WriteI2C_Byte(0x3e,0x0a); - HDMI_WriteI2C_Byte(0x0F,0x2B); -+ printk("%s HDMI audio packet setup: 48k N=0x1800\n", LOG_FLAG); - } - - void AudioSpdifEn(void) -@@ -500,11 +568,8 @@ - if (mipi_det_fail_count < 0xff) - mipi_det_fail_count++; - -- if (mipi_det_fail_count >= 10 && mipi_relock_count < 5) { -- mipi_relock_count++; -- mipi_det_fail_count = 0; -- LT8912B_MIPI_Relock(); -- } -+ if (mipi_det_fail_count == 10) -+ printk("%s MIPI input invalid, skip auto relock\n", LOG_FLAG); - } else { - mipi_det_fail_count = 0; - } -@@ -525,7 +590,7 @@ - video_valid = true; - printk("%s videoformat = VESA_1280x800_60\n",LOG_FLAG); - } -- else if(Vsync_H == 0x04 && Vsync_L <= 0xb6&&Vsync_L >= 0x63)//0x4b2 -+ else if(Vsync_H == 0x04 && Vsync_L <= 0x67&&Vsync_L >= 0x63)//0x465 - { - video = &video_1920x1080_60Hz; - video_valid = true; -@@ -544,9 +609,21 @@ - if (video_valid) { - mipi_det_fail_count = 0; - mipi_relock_count = 0; -+ mipi_video_ready = 1; -+ DDSConfig(video); - MIPI_Video_Setup(video); - AviInfoframe(video); - MIPIRxLogicRes(); -+ -+ #ifdef _hdmi_output -+ if (LT8912_Get_HPD() && !Tx_HPD) { -+ msleep(50); -+ HdmiOutput(1); -+ Tx_HPD = 1; -+ printk("%s HDMI output enabled after valid MIPI video\n", -+ LOG_FLAG); -+ } -+ #endif - } - } - -@@ -716,7 +793,7 @@ - HDMIPllAnalog(); - MipiAnalog(); - MipiBasicSet(); -- DDSConfig(); -+ DDSConfig(&video_1920x1080_60Hz); - MIPI_Video_Setup(&video_1920x1080_60Hz); - MIPI_Input_det(); - AudioIIsEn(); -@@ -726,7 +803,7 @@ - lt8912_check_dds(); // can be removed when debug stage. - #endif - -- #ifdef _lvds_bypass -+ #ifdef _lvds_output - lvds_output_cfg(); - LvdsOutput(1); - #endif -@@ -737,7 +814,7 @@ - ///////////////////////////////////////////////////////////// - - #ifdef _hdmi_output -- if(LT8912_Get_HPD()) -+ if(LT8912_Get_HPD() && mipi_video_ready) - { - if(!Tx_HPD) - { -@@ -769,7 +846,7 @@ - #ifdef _hdmi_output - if(LT8912_Get_HPD()) - { -- if(!Tx_HPD) -+ if(mipi_video_ready && !Tx_HPD) - { - LT8912B_Suspend(0); - HdmiOutput(1); diff --git a/HDMI/LT8912B-HDMI.patch b/HDMI/LT8912B-HDMI.patch deleted file mode 100644 index 16538c92e..000000000 --- a/HDMI/LT8912B-HDMI.patch +++ /dev/null @@ -1,3596 +0,0 @@ -LT8912B HDMI bring-up patch for UIS7885-2H10 - -Generated from current workspace HDMI-related source changes. -Apply from source_sync_rls_25c with: - patch -p1 < ../HDMI/LT8912B-HDMI.patch - -diff --git a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4.bb b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4.bb -index 664cdf2e..a1aa82ad 100755 ---- a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4.bb -+++ b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4.bb -@@ -22,6 +22,7 @@ SRC_URI = "file://serial.cfg \ - file://kernel-config/8021q_vlan.cfg \ - ${KERNEL_MACHINE_PATCH} \ - ${@bb.utils.contains('USERDEBUG', 'userdebug', 'file://userdebug.cfg', 'file://user.cfg', d)} \ -+ file://enable-8912.cfg \ - " - - PV = "5.4" -diff --git a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts -index 02c344bd..3396f85d 100755 ---- a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts -+++ b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts -@@ -7,7 +7,7 @@ - #include - #include "lcd/lcd_g40396_truly_mipi_fhd.dtsi" - #include "lcd/lcd_nt36672e_truly_mipi_fhd_nodsc.dtsi" --#include "lcd/lcd_dummy_mipi.dtsi" -+#include "lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi" - #include "tp/ums9620-tp.dtsi" - #include - #include -@@ -223,8 +223,8 @@ - compatible = "unisoc,marlin3lite_sdio"; - m2-wakeup-ap-gpios = <&ap_gpio 128 GPIO_ACTIVE_LOW>; - reset-gpios = <&ap_gpio 172 GPIO_ACTIVE_LOW>; -- enable-gpios = <&ap_gpio 171 GPIO_ACTIVE_LOW>; -- m2-to-ap-irq-gpios = <&ap_gpio 173 GPIO_ACTIVE_LOW>; -+ enable-gpios = <&ap_gpio 151 GPIO_ACTIVE_LOW>; -+ m2-to-ap-irq-gpios = <&ap_gpio 177 GPIO_ACTIVE_LOW>; - xtal-26m-clk-type = "TCXO"; - avdd12-supply = <&vddwcn>; - avdd33-supply = <&vddwifipa>; -@@ -234,8 +234,8 @@ - clocks = <&aonapb_gate CLK_AUX0>, - <&ext_32k>, - <&aonapb_gate CLK_AUX0_EB>; -- extcon = <&sdio1>; -- sdhci-name = <&sdio1>; -+ extcon = <&sdio2>; -+ sdhci-name = <&sdio2>; - sprd,btwf-file-name = "/dev/block/by-name/wcnmodem"; - sprd,gnss-file-name = "/vendor/firmware/gnssmodem.bin"; - adma-tx; -@@ -354,7 +354,7 @@ - }; - - &chosen { -- bootargs = "earlycon console=ttyS1,921600n8 loglevel=1 init=/sbin/init root=/dev/mmcblk0p31 rootfstype=ext4 ro rootwait printk.devkmsg=on sprdboot.boot_devices=soc/soc:ap-ahb/20600000.sdio dummy_hcd.num=0 swiotlb=1 initcall_debug=1"; -+ bootargs = "earlycon console=ttyS1,921600n8 loglevel=1 init=/sbin/init root=/dev/mmcblk0p31 rootfstype=ext4 ro rootwait printk.devkmsg=on dummy_hcd.num=0 swiotlb=1 initcall_debug=1"; - bootargs_ext = "sprdboot.hardware=uis7885_2h10 sprdboot.dtbo_idx=0"; - }; - -@@ -407,13 +407,6 @@ - #address-cells = <1>; - #size-cells = <0>; - -- ucp1301_spk: ucp1301@58 { -- compatible = "sprd,ucp1301-spk"; -- reg = <0x58>; -- reset-gpios = <&ap_gpio 120 GPIO_ACTIVE_HIGH>; -- #sound-dai-cells = <1>; -- }; -- - bq2560x_chg: charger@6b { - compatible = "ti,bq2560x_chg"; - reg = <0x6b>; -@@ -426,7 +419,6 @@ - bq2597x_chg: charger@65 { - compatible = "ti,bq2597x-standalone"; - reg = <0x65>; -- irq-gpio = <&ap_gpio 193 GPIO_ACTIVE_LOW>; - - ti,bq2597x,bus-therm-disable = <1>; - ti,bq2597x,regulation-disable = <1>; -@@ -472,7 +464,36 @@ - - &usb { - extcon = <&extcon_gpio>, <&pmic_typec>; -- vbus-supply = <&vddvbus>; -+ /*vbus-supply = <&vddvbus>;*/ -+ status = "okay"; -+}; -+ -+&ap_gpio { -+ hdmi_5v_en { -+ gpio-hog; -+ gpios = <187 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "hdmi-5v-en"; -+ }; -+ -+ rtl8111_3v3_en { -+ gpio-hog; -+ gpios = <147 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "rtl8111-3v3-en"; -+ }; -+ -+ serial_level_en { -+ gpio-hog; -+ gpios = <140 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "serial-level-en"; -+ }; -+}; -+ -+&pwms { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm2_pwmc>; - status = "okay"; - }; - -@@ -486,7 +507,7 @@ - - &usb3 { - extcon = <&extcon_gpio>, <&pmic_typec>; -- vbus-supply = <&vddvbus>; -+ /*vbus-supply = <&vddvbus>;*/ - status = "okay"; - }; - -@@ -523,7 +544,14 @@ - }; - - &sdio0 { -- cd-gpios = <&eic_sync 35 GPIO_ACTIVE_HIGH>; -+ cd-gpios = <&eic_sync 35 GPIO_ACTIVE_LOW>; -+}; -+ -+&pmic_typec { -+ /*usb-channel-switch-hub;*/ -+ usb-hub-en = <&ap_gpio 41 GPIO_ACTIVE_HIGH>; -+ usb-hub-5v-en = <&ap_gpio 146 GPIO_ACTIVE_HIGH>; -+ usb-channel-sw = <&ap_gpio 188 GPIO_ACTIVE_HIGH>; - }; - - &pmic_fgu { -@@ -564,10 +592,7 @@ - }; - - &panel { -- sprd,backlight = <&pwm_backlight>; -- avdd-gpio = <&ap_gpio 192 GPIO_ACTIVE_HIGH>; -- avee-gpio = <&ap_gpio 191 GPIO_ACTIVE_HIGH>; -- reset-gpio = <&ap_gpio 11 GPIO_ACTIVE_HIGH>; -+ sprd,backlight = <&pwm_backlight>; - }; - - &dpu { -@@ -637,76 +662,39 @@ - }; - - &i2c0 { -- status = "okay"; -+ status = "disabled"; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -- -- sensor_main: sensor-main@20 { -- compatible = "sprd,sensor-main"; -- reg = <0x20>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR0>,<&mm_gate CLK_SENSOR0_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama0>; -- vddcamd-supply = <&vddcamd0>; -- vddcammot-supply = <&vddcammot0>; -- reset-gpios = <&ap_gpio 40 0>; -- power-down-gpios = <&ap_gpio 46 0>; -- sprd,phyid = <0>; -- csi = <&csi0>; -- power-domains = <&mm_domain>; -- }; -- -- sensor_sub: sensor-sub@5a { -- compatible = "sprd,sensor-sub"; -- reg = <0x5a>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR0>,<&mm_gate CLK_SENSOR0_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama0>; -- vddcamd-supply = <&vddcamd0>; -- vddcammot-supply = <&vddcammot0>; -- reset-gpios = <&ap_gpio 39 0>; -- power-down-gpios = <&ap_gpio 45 0>; -- sprd,phyid = <1>; -- csi = <&csi1>; -- power-domains = <&mm_domain>; -- }; - }; - - &i2c1 { -+ status = "disabled"; -+ clock-frequency = <400000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+}; -+ -+&i2c2 { - status = "okay"; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - -- sensor_main2: sensor-main2@20 { -- compatible = "sprd,sensor-main2"; -- reg = <0x20>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR1>,<&mm_gate CLK_SENSOR1_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama1>; -- vddcamd-supply = <&vddcamd1>; -- avdd-gpios = <&ap_gpio 79 0>; -- reset-gpios = <&ap_gpio 41 0>; -- power-down-gpios = <&ap_gpio 47 0>; -- sprd,phyid = <3>;/*6*/ -- csi = <&csi3>; -- power-domains = <&mm_domain>; -+ lt8912b: lt8912b@48 { -+ compatible = "lontium,lt8912b"; -+ reg = <0x48>; -+ power-gpios = <&ap_gpio 99 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&ap_gpio 11 GPIO_ACTIVE_HIGH>; -+ interrupt-gpios = <&ap_gpio 132 GPIO_ACTIVE_HIGH>; -+ -+ lt8912b_addr_1: lt8912b_addr_1@49 { -+ addr_1_reg = /bits/ 8 <0x49>; -+ }; -+ -+ lt8912b_addr_2: lt8912b_addr_2@4a { -+ addr_2_reg = /bits/ 8 <0x4a>; -+ }; - }; - }; - -@@ -716,9 +704,9 @@ - #address-cells = <1>; - #size-cells = <0>; - -- sensor_main3: sensor-main3@20 { -- compatible = "sprd,sensor-main3"; -- reg = <0x20>; -+ sensor_imx258_a: sensor-imx258-a@1a { -+ compatible = "sprd,sensor-main"; -+ reg = <0x1a>; - clock-names = "clk_src","sensor_eb", - "clk_96m","clk_64m", - "clk_51m2","clk_48m","clk_26m"; -@@ -726,15 +714,13 @@ - <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, - <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; - vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama2>; -- vddcamd-supply = <&vddcamd2>; -- vddcammot-supply = <&vddcammot1>; -- mot-gpios = <&ap_gpio 78 0>; - reset-gpios = <&ap_gpio 42 0>; -- sprd,phyid = <2>;/*4*/ -+ power-down-gpios = <&ap_gpio 47 0>; -+ sprd,phyid = <2>; - csi = <&csi2>; - power-domains = <&mm_domain>; - }; -+ - }; - - &i2c5 { -@@ -742,44 +728,6 @@ - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -- -- sensor_sub2: sensor-sensor_sub2@2a { -- compatible = "sprd,sensor-sub2"; -- reg = <0x2a>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR1>,<&mm_gate CLK_SENSOR1_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama1>; -- vddcamd-supply = <&vddcamd1>; -- reset-gpios = <&ap_gpio 44 0>; -- power-down-gpios = <&ap_gpio 50 0>; -- sprd,phyid = <5>; -- csi = <&csi2>; -- power-domains = <&mm_domain>; -- }; -- -- sensor_sub3: sensor-sensor_sub3@2e { -- compatible = "sprd,sensor-sub3"; -- reg = <0x2e>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR3>,<&mm_gate CLK_SENSOR3_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama2>; -- vddcamd-supply = <&vddcamd2>; -- reset-gpios = <&ap_gpio 43 0>; -- power-down-gpios = <&ap_gpio 49 0>; -- sprd,phyid = <7>; -- csi = <&csi3>; -- power-domains = <&mm_domain>; -- }; - }; - - &i2c6 { -@@ -788,10 +736,19 @@ - #address-cells = <1>; - #size-cells = <0>; - -+ aw87xxx_pa@58 { -+ compatible = "awinic,aw87xxx_pa"; -+ reg = <0x58>; -+ /* reset-gpio = <&ap_gpio 1 0>;*/ -+ dev_index = < 0 >; -+ status = "okay"; -+ }; -+ - flash_ic: flash-ic@63 { - compatible = "sprd,flash-ocp8137"; - reg = <0x63>; - sprd,flash-ic = <8137>; -+ status = "disabled"; - sprd,torch = <1>; - sprd,preflash = <1>; - sprd,highlight = <1>; -@@ -806,54 +763,99 @@ - }; - }; - -+&i2c7 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ wm8960: codec@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ #sound-dai-cells = <0>; -+ wlf,shared-lrclk; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart3 { -+ status = "okay"; -+}; -+ - &pdm_dmic { - status = "okay"; - }; - -+&spi0 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_grp &spi0_di_grp>; -+ num-chipselect = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ spidev0: spidev@0 { -+ compatible = "rohm,dh2228fv"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&i2s0 { -+ compatible = "unisoc,i2s"; -+ status = "okay"; -+ -+ sprd,config_type = "i2s"; -+ sprd,fs = <48000>; -+ sprd,bus_type = <0>; -+ sprd,slave_mode = <0>; -+ sprd,rtx_mode = <3>; -+ sprd,byte_per_chan = <2>; -+ sprd,lsb = <0>; -+ sprd,lrck = <0>; -+ sprd,clk_inv = <0>; -+ sprd,tx_watermark = <12>; -+ sprd,rx_watermark = <20>; -+}; -+ -+&vbc_v4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ap_iis0_5>; -+}; -+ -+&sound_sprd_ap_alliis { -+ status = "okay"; -+ -+ sprd-audio-card,dai-link@0 { -+ format = "i2s"; -+ bitclock-master = <&wm8960_cpu>; -+ frame-master = <&wm8960_cpu>; -+ -+ plat { -+ sound-dai = <&sprd_pcm_iis>; -+ }; -+ -+ wm8960_cpu: cpu { -+ sound-dai = <&i2s0>; -+ }; -+ -+ codec { -+ sound-dai = <&wm8960>; -+ }; -+ }; -+}; -+ - &sprd_headset { - status = "okay"; -- extcon = <&pmic_typec>; -- mic-gpios = <&ap_gpio 62 GPIO_ACTIVE_HIGH>; -- lr-gpios = <&ap_gpio 61 GPIO_ACTIVE_HIGH>; -- sprd,3pole-adc-threshold = <112>; -+ sprd,jack-type = <1>; /* 0: normal-open jack; 1: normal-close jack */ - }; - - &sound_vbc_v4_sprd_codec { - status = "okay"; -- sprd-audio-card,routing = -- "HPMIC Pin", "HP Mic Jack", -- "MIC Pin", "Mic Jack", -- "MIC2 Pin", "Aux Mic Jack", -- "MIC3 Pin", "Aux Mic2 Jack", -- "HeadPhone Jack", "HP Pin", -- "Ext Spk", "SPK Pin", -- "UCP1301 SPK ON", "SPK Pin", -- "Ext Spk", "UCP1301 SPK", -- "PDM DMIC2 ON", "SPK Pin", -- "Ext Spk", "PDM_DMIC2", -- "DMIC Pin", "DMic Jack", -- "DMIC1 Pin", "DMic1 Jack", -- "Ext Ear", "EAR Pin"; -- -- /* 35: ucp1301 normal ap01 */ -- sprd-audio-card,dai-link@53 { -- ignore-suspend = <1>; -- link-name = "BE_NORMAL_AP01_UCPSPK"; -- stream-name = "BE_ST_NORMAL_AP01_UCPSPK"; -- no-pcm = <1>; -- dpcm-playback = <1>; -- be-id = <0>; -- dai-format = "i2s"; -- plat { -- sound-dai = <&sprd_route_pcm>; -- }; -- cpu { -- sound-dai = <&vbc_v4 31>; -- }; -- codec { -- sound-dai = <&ucp1301_spk 0>; -- }; -- }; -+ extral-iic-pa-cnt = <1>; - - /* - * node 54 and node 55 (index 36 and 37) are reserved for -@@ -950,4 +952,32 @@ - pins = "QOGIRN6PRO_KEYOUT1"; - function = "func4"; - }; -+ -+ pwm2_pwmc: pwmc { -+ pins = "QOGIRN6PRO_PWMC"; -+ function = "func1"; -+ }; -+ -+ spi0_grp: spi0_grp { -+ pins = "QOGIRN6PRO_SPI0_CLK", -+ "QOGIRN6PRO_SPI0_DO", -+ "QOGIRN6PRO_SPI0_CSN"; -+ function = "func1"; -+ }; -+ -+ spi0_di_grp: spi0-di-grp { -+ pins = "QOGIRN6PRO_SPI0_DI"; -+ function = "func1"; -+ input-enable; -+ bias-disable; -+ }; -+ -+ iis1_pins: iis1-grp { -+ pins = "QOGIRN6PRO_IIS1CLK", -+ "QOGIRN6PRO_IIS1LRCK", -+ "QOGIRN6PRO_IIS1DO", -+ "QOGIRN6PRO_IIS1DI"; -+ function = "func1"; -+ bias-disable; -+ }; - }; -diff --git a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/enable-8912.cfg b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/enable-8912.cfg -new file mode 100644 ---- a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/enable-8912.cfg -+++ b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/enable-8912.cfg -@@ -0,0 +1 @@ -+CONFIG_LT8912B=y -\ No newline at end of file -diff --git a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -new file mode 100644 ---- a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -0,0 +1,54 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * LT8912B MIPI-DSI to HDMI 1080p dummy panel config. -+ */ -+ -+/ { -+ fragment { -+ target-path = "/"; -+ __overlay__ { -+ lcds { -+ lcd_dummy_mipi_hd: lcd_dummy_mipi_hd { -+ sprd,dsi-work-mode = <2>; /* video pulse mode */ -+ sprd,dsi-lane-number = <4>; -+ sprd,dsi-color-format = "rgb888"; -+ -+ sprd,phy-bit-clock = <1200000>; /* kbps 921600 1200000 */ -+ sprd,phy-escape-clock = <20000>; /* kHz */ -+ sprd,video-lp-cmd-enable = <0>; -+ sprd,hporch-lp-disable = <1>; -+ sprd,width-mm = <121>; -+ sprd,height-mm = <68>; -+ sprd,esd-check-enable = <0>; -+ sprd,esd-check-mode = <1>; -+ sprd,esd-check-period = <1000>; -+ sprd,panel-if-type = <2>; -+ sprd,reset-on-sequence = <1 5>, <0 5>, <1 5>, <0 5>, <1 20>; -+ sprd,reset-off-sequence = <0 20>; -+ sprd,initial-command = [ -+ ]; -+ sprd,sleep-in-command = [ -+ ]; -+ sprd,sleep-out-command = [ -+ ]; -+ -+ display-timings { -+ native-mode = <<8912b_1080p_timing0>; -+ -+ lt8912b_1080p_timing0: timing0 { -+ clock-frequency = <153600000>; -+ hactive = <1920>; -+ vactive = <1080>; -+ hfront-porch = <88>; -+ hsync-len = <44>; -+ hback-porch = <148>; -+ vfront-porch = <56>; -+ vsync-len = <6>; -+ vback-porch = <60>; -+ }; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -diff --git a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/uis7885-2h10-overlay.dts b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/uis7885-2h10-overlay.dts -index 6faf7c901cf3..3396f85d05d4 100755 ---- a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/uis7885-2h10-overlay.dts -+++ b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/uis7885-2h10-overlay.dts -@@ -7,7 +7,7 @@ - #include - #include "lcd/lcd_g40396_truly_mipi_fhd.dtsi" - #include "lcd/lcd_nt36672e_truly_mipi_fhd_nodsc.dtsi" --#include "lcd/lcd_dummy_mipi.dtsi" -+#include "lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi" - #include "tp/ums9620-tp.dtsi" - #include - #include -@@ -223,8 +223,8 @@ - compatible = "unisoc,marlin3lite_sdio"; - m2-wakeup-ap-gpios = <&ap_gpio 128 GPIO_ACTIVE_LOW>; - reset-gpios = <&ap_gpio 172 GPIO_ACTIVE_LOW>; -- enable-gpios = <&ap_gpio 171 GPIO_ACTIVE_LOW>; -- m2-to-ap-irq-gpios = <&ap_gpio 173 GPIO_ACTIVE_LOW>; -+ enable-gpios = <&ap_gpio 151 GPIO_ACTIVE_LOW>; -+ m2-to-ap-irq-gpios = <&ap_gpio 177 GPIO_ACTIVE_LOW>; - xtal-26m-clk-type = "TCXO"; - avdd12-supply = <&vddwcn>; - avdd33-supply = <&vddwifipa>; -@@ -234,8 +234,8 @@ - clocks = <&aonapb_gate CLK_AUX0>, - <&ext_32k>, - <&aonapb_gate CLK_AUX0_EB>; -- extcon = <&sdio1>; -- sdhci-name = <&sdio1>; -+ extcon = <&sdio2>; -+ sdhci-name = <&sdio2>; - sprd,btwf-file-name = "/dev/block/by-name/wcnmodem"; - sprd,gnss-file-name = "/vendor/firmware/gnssmodem.bin"; - adma-tx; -@@ -354,7 +354,7 @@ - }; - - &chosen { -- bootargs = "earlycon console=ttyS1,115200n8 loglevel=1 init=/sbin/init root=/dev/mmcblk0p31 rootfstype=ext4 ro rootwait printk.devkmsg=on sprdboot.boot_devices=soc/soc:ap-ahb/20600000.sdio dummy_hcd.num=0 swiotlb=1 initcall_debug=1"; -+ bootargs = "earlycon console=ttyS1,921600n8 loglevel=1 init=/sbin/init root=/dev/mmcblk0p31 rootfstype=ext4 ro rootwait printk.devkmsg=on dummy_hcd.num=0 swiotlb=1 initcall_debug=1"; - bootargs_ext = "sprdboot.hardware=uis7885_2h10 sprdboot.dtbo_idx=0"; - }; - -@@ -407,13 +407,6 @@ - #address-cells = <1>; - #size-cells = <0>; - -- ucp1301_spk: ucp1301@58 { -- compatible = "sprd,ucp1301-spk"; -- reg = <0x58>; -- reset-gpios = <&ap_gpio 120 GPIO_ACTIVE_HIGH>; -- #sound-dai-cells = <1>; -- }; -- - bq2560x_chg: charger@6b { - compatible = "ti,bq2560x_chg"; - reg = <0x6b>; -@@ -426,7 +419,6 @@ - bq2597x_chg: charger@65 { - compatible = "ti,bq2597x-standalone"; - reg = <0x65>; -- irq-gpio = <&ap_gpio 193 GPIO_ACTIVE_LOW>; - - ti,bq2597x,bus-therm-disable = <1>; - ti,bq2597x,regulation-disable = <1>; -@@ -472,7 +464,36 @@ - - &usb { - extcon = <&extcon_gpio>, <&pmic_typec>; -- vbus-supply = <&vddvbus>; -+ /*vbus-supply = <&vddvbus>;*/ -+ status = "okay"; -+}; -+ -+&ap_gpio { -+ hdmi_5v_en { -+ gpio-hog; -+ gpios = <187 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "hdmi-5v-en"; -+ }; -+ -+ rtl8111_3v3_en { -+ gpio-hog; -+ gpios = <147 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "rtl8111-3v3-en"; -+ }; -+ -+ serial_level_en { -+ gpio-hog; -+ gpios = <140 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "serial-level-en"; -+ }; -+}; -+ -+&pwms { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm2_pwmc>; - status = "okay"; - }; - -@@ -486,7 +507,7 @@ - - &usb3 { - extcon = <&extcon_gpio>, <&pmic_typec>; -- vbus-supply = <&vddvbus>; -+ /*vbus-supply = <&vddvbus>;*/ - status = "okay"; - }; - -@@ -523,7 +544,14 @@ - }; - - &sdio0 { -- cd-gpios = <&eic_sync 35 GPIO_ACTIVE_HIGH>; -+ cd-gpios = <&eic_sync 35 GPIO_ACTIVE_LOW>; -+}; -+ -+&pmic_typec { -+ /*usb-channel-switch-hub;*/ -+ usb-hub-en = <&ap_gpio 41 GPIO_ACTIVE_HIGH>; -+ usb-hub-5v-en = <&ap_gpio 146 GPIO_ACTIVE_HIGH>; -+ usb-channel-sw = <&ap_gpio 188 GPIO_ACTIVE_HIGH>; - }; - - &pmic_fgu { -@@ -534,6 +562,10 @@ - fgu-capacity-track; - phys = <&ssphy>; - -+ sprd,relax-counter-threshold = <580>; -+ sprd,relax-current-threshold = <30>; -+ sprd,capacity-sleep-calibration; -+ - sprd,capacity-boot-calibration; - sprd,capacity-charge-cycle; - sprd,basp; -@@ -560,10 +592,7 @@ - }; - - &panel { -- sprd,backlight = <&pwm_backlight>; -- avdd-gpio = <&ap_gpio 192 GPIO_ACTIVE_HIGH>; -- avee-gpio = <&ap_gpio 191 GPIO_ACTIVE_HIGH>; -- reset-gpio = <&ap_gpio 11 GPIO_ACTIVE_HIGH>; -+ sprd,backlight = <&pwm_backlight>; - }; - - &dpu { -@@ -608,6 +637,14 @@ - status = "disabled"; - }; - -+&vddsim0 { -+ status = "disabled"; -+}; -+ -+&vddsim1 { -+ status = "disabled"; -+}; -+ - &avdd12 { - regulator-always-on; - }; -@@ -625,76 +662,39 @@ - }; - - &i2c0 { -- status = "okay"; -+ status = "disabled"; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -- -- sensor_main: sensor-main@20 { -- compatible = "sprd,sensor-main"; -- reg = <0x20>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR0>,<&mm_gate CLK_SENSOR0_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama0>; -- vddcamd-supply = <&vddcamd0>; -- vddcammot-supply = <&vddcammot0>; -- reset-gpios = <&ap_gpio 40 0>; -- power-down-gpios = <&ap_gpio 46 0>; -- sprd,phyid = <0>; -- csi = <&csi0>; -- power-domains = <&mm_domain>; -- }; -- -- sensor_sub: sensor-sub@5a { -- compatible = "sprd,sensor-sub"; -- reg = <0x5a>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR0>,<&mm_gate CLK_SENSOR0_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama0>; -- vddcamd-supply = <&vddcamd0>; -- vddcammot-supply = <&vddcammot0>; -- reset-gpios = <&ap_gpio 39 0>; -- power-down-gpios = <&ap_gpio 45 0>; -- sprd,phyid = <1>; -- csi = <&csi1>; -- power-domains = <&mm_domain>; -- }; - }; - - &i2c1 { -+ status = "disabled"; -+ clock-frequency = <400000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+}; -+ -+&i2c2 { - status = "okay"; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - -- sensor_main2: sensor-main2@20 { -- compatible = "sprd,sensor-main2"; -- reg = <0x20>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR1>,<&mm_gate CLK_SENSOR1_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama1>; -- vddcamd-supply = <&vddcamd1>; -- avdd-gpios = <&ap_gpio 79 0>; -- reset-gpios = <&ap_gpio 41 0>; -- power-down-gpios = <&ap_gpio 47 0>; -- sprd,phyid = <3>;/*6*/ -- csi = <&csi3>; -- power-domains = <&mm_domain>; -+ lt8912b: lt8912b@48 { -+ compatible = "lontium,lt8912b"; -+ reg = <0x48>; -+ power-gpios = <&ap_gpio 99 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&ap_gpio 11 GPIO_ACTIVE_HIGH>; -+ interrupt-gpios = <&ap_gpio 132 GPIO_ACTIVE_HIGH>; -+ -+ lt8912b_addr_1: lt8912b_addr_1@49 { -+ addr_1_reg = /bits/ 8 <0x49>; -+ }; -+ -+ lt8912b_addr_2: lt8912b_addr_2@4a { -+ addr_2_reg = /bits/ 8 <0x4a>; -+ }; - }; - }; - -@@ -704,9 +704,9 @@ - #address-cells = <1>; - #size-cells = <0>; - -- sensor_main3: sensor-main3@20 { -- compatible = "sprd,sensor-main3"; -- reg = <0x20>; -+ sensor_imx258_a: sensor-imx258-a@1a { -+ compatible = "sprd,sensor-main"; -+ reg = <0x1a>; - clock-names = "clk_src","sensor_eb", - "clk_96m","clk_64m", - "clk_51m2","clk_48m","clk_26m"; -@@ -714,15 +714,13 @@ - <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, - <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; - vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama2>; -- vddcamd-supply = <&vddcamd2>; -- vddcammot-supply = <&vddcammot1>; -- mot-gpios = <&ap_gpio 78 0>; - reset-gpios = <&ap_gpio 42 0>; -- sprd,phyid = <2>;/*4*/ -+ power-down-gpios = <&ap_gpio 47 0>; -+ sprd,phyid = <2>; - csi = <&csi2>; - power-domains = <&mm_domain>; - }; -+ - }; - - &i2c5 { -@@ -730,44 +728,6 @@ - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -- -- sensor_sub2: sensor-sensor_sub2@2a { -- compatible = "sprd,sensor-sub2"; -- reg = <0x2a>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR1>,<&mm_gate CLK_SENSOR1_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama1>; -- vddcamd-supply = <&vddcamd1>; -- reset-gpios = <&ap_gpio 44 0>; -- power-down-gpios = <&ap_gpio 50 0>; -- sprd,phyid = <5>; -- csi = <&csi2>; -- power-domains = <&mm_domain>; -- }; -- -- sensor_sub3: sensor-sensor_sub3@2e { -- compatible = "sprd,sensor-sub3"; -- reg = <0x2e>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR3>,<&mm_gate CLK_SENSOR3_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama2>; -- vddcamd-supply = <&vddcamd2>; -- reset-gpios = <&ap_gpio 43 0>; -- power-down-gpios = <&ap_gpio 49 0>; -- sprd,phyid = <7>; -- csi = <&csi3>; -- power-domains = <&mm_domain>; -- }; - }; - - &i2c6 { -@@ -776,10 +736,19 @@ - #address-cells = <1>; - #size-cells = <0>; - -+ aw87xxx_pa@58 { -+ compatible = "awinic,aw87xxx_pa"; -+ reg = <0x58>; -+ /* reset-gpio = <&ap_gpio 1 0>;*/ -+ dev_index = < 0 >; -+ status = "okay"; -+ }; -+ - flash_ic: flash-ic@63 { - compatible = "sprd,flash-ocp8137"; - reg = <0x63>; - sprd,flash-ic = <8137>; -+ status = "disabled"; - sprd,torch = <1>; - sprd,preflash = <1>; - sprd,highlight = <1>; -@@ -794,54 +763,99 @@ - }; - }; - -+&i2c7 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ wm8960: codec@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ #sound-dai-cells = <0>; -+ wlf,shared-lrclk; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart3 { -+ status = "okay"; -+}; -+ - &pdm_dmic { - status = "okay"; - }; - -+&spi0 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_grp &spi0_di_grp>; -+ num-chipselect = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ spidev0: spidev@0 { -+ compatible = "rohm,dh2228fv"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&i2s0 { -+ compatible = "unisoc,i2s"; -+ status = "okay"; -+ -+ sprd,config_type = "i2s"; -+ sprd,fs = <48000>; -+ sprd,bus_type = <0>; -+ sprd,slave_mode = <0>; -+ sprd,rtx_mode = <3>; -+ sprd,byte_per_chan = <2>; -+ sprd,lsb = <0>; -+ sprd,lrck = <0>; -+ sprd,clk_inv = <0>; -+ sprd,tx_watermark = <12>; -+ sprd,rx_watermark = <20>; -+}; -+ -+&vbc_v4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ap_iis0_5>; -+}; -+ -+&sound_sprd_ap_alliis { -+ status = "okay"; -+ -+ sprd-audio-card,dai-link@0 { -+ format = "i2s"; -+ bitclock-master = <&wm8960_cpu>; -+ frame-master = <&wm8960_cpu>; -+ -+ plat { -+ sound-dai = <&sprd_pcm_iis>; -+ }; -+ -+ wm8960_cpu: cpu { -+ sound-dai = <&i2s0>; -+ }; -+ -+ codec { -+ sound-dai = <&wm8960>; -+ }; -+ }; -+}; -+ - &sprd_headset { - status = "okay"; -- extcon = <&pmic_typec>; -- mic-gpios = <&ap_gpio 62 GPIO_ACTIVE_HIGH>; -- lr-gpios = <&ap_gpio 61 GPIO_ACTIVE_HIGH>; -- sprd,3pole-adc-threshold = <112>; -+ sprd,jack-type = <1>; /* 0: normal-open jack; 1: normal-close jack */ - }; - - &sound_vbc_v4_sprd_codec { - status = "okay"; -- sprd-audio-card,routing = -- "HPMIC Pin", "HP Mic Jack", -- "MIC Pin", "Mic Jack", -- "MIC2 Pin", "Aux Mic Jack", -- "MIC3 Pin", "Aux Mic2 Jack", -- "HeadPhone Jack", "HP Pin", -- "Ext Spk", "SPK Pin", -- "UCP1301 SPK ON", "SPK Pin", -- "Ext Spk", "UCP1301 SPK", -- "PDM DMIC2 ON", "SPK Pin", -- "Ext Spk", "PDM_DMIC2", -- "DMIC Pin", "DMic Jack", -- "DMIC1 Pin", "DMic1 Jack", -- "Ext Ear", "EAR Pin"; -- -- /* 35: ucp1301 normal ap01 */ -- sprd-audio-card,dai-link@53 { -- ignore-suspend = <1>; -- link-name = "BE_NORMAL_AP01_UCPSPK"; -- stream-name = "BE_ST_NORMAL_AP01_UCPSPK"; -- no-pcm = <1>; -- dpcm-playback = <1>; -- be-id = <0>; -- dai-format = "i2s"; -- plat { -- sound-dai = <&sprd_route_pcm>; -- }; -- cpu { -- sound-dai = <&vbc_v4 31>; -- }; -- codec { -- sound-dai = <&ucp1301_spk 0>; -- }; -- }; -+ extral-iic-pa-cnt = <1>; - - /* - * node 54 and node 55 (index 36 and 37) are reserved for -@@ -938,4 +952,32 @@ - pins = "QOGIRN6PRO_KEYOUT1"; - function = "func4"; - }; -+ -+ pwm2_pwmc: pwmc { -+ pins = "QOGIRN6PRO_PWMC"; -+ function = "func1"; -+ }; -+ -+ spi0_grp: spi0_grp { -+ pins = "QOGIRN6PRO_SPI0_CLK", -+ "QOGIRN6PRO_SPI0_DO", -+ "QOGIRN6PRO_SPI0_CSN"; -+ function = "func1"; -+ }; -+ -+ spi0_di_grp: spi0-di-grp { -+ pins = "QOGIRN6PRO_SPI0_DI"; -+ function = "func1"; -+ input-enable; -+ bias-disable; -+ }; -+ -+ iis1_pins: iis1-grp { -+ pins = "QOGIRN6PRO_IIS1CLK", -+ "QOGIRN6PRO_IIS1LRCK", -+ "QOGIRN6PRO_IIS1DO", -+ "QOGIRN6PRO_IIS1DI"; -+ function = "func1"; -+ bias-disable; -+ }; - }; -diff --git a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/dsi/sprd_dsi_api.c b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/dsi/sprd_dsi_api.c -index d7ab66e11d6c..d4600032cd51 100644 ---- a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/dsi/sprd_dsi_api.c -+++ b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/dsi/sprd_dsi_api.c -@@ -4,8 +4,10 @@ - */ - - #include -+#include - - #include "sprd_dsi_hal.h" -+#include "core/dsi_ctrl_r1p0.h" - - static int dsi_wait_tx_payload_fifo_empty(struct sprd_dsi *dsi) - { -@@ -140,6 +142,29 @@ static u16 round_video_size(int coding, u16 video_size) - return video_size; - } - -+static void sprd_dsi_dump_video_regs(struct sprd_dsi *dsi, const char *tag) -+{ -+ struct dsi_reg *reg = (struct dsi_reg *)dsi->ctx.base; -+ -+ pr_info("DSI regs[%s]: VERSION=0x%08x SOFT_RESET=0x%08x MODE_CFG=0x%08x VCID=0x%08x DPI_FMT=0x%08x\n", -+ tag, readl(®->DSI_VERSION), readl(®->SOFT_RESET), -+ readl(®->DSI_MODE_CFG), readl(®->VIRTUAL_CHANNEL_ID), -+ readl(®->DPI_VIDEO_FORMAT)); -+ pr_info("DSI regs[%s]: VID_PKT=0x%08x HBLK=0x%08x HLINE=0x%08x VBLK=0x%08x VACT=0x%08x VID_MODE=0x%08x NULLPKT=0x%08x SIG_DELAY=0x%08x\n", -+ tag, readl(®->VIDEO_PKT_CONFIG), -+ readl(®->VIDEO_LINE_HBLK_TIME), -+ readl(®->VIDEO_LINE_TIME), readl(®->VIDEO_VBLK_LINES), -+ readl(®->VIDEO_VACTIVE_LINES), readl(®->VID_MODE_CFG), -+ readl(®->VIDEO_NULLPKT_SIZE), -+ readl(®->VIDEO_SIG_DELAY_CONFIG)); -+ pr_info("DSI regs[%s]: PHY_STATUS=0x%08x PHY_LANE_NUM=0x%08x PHY_CLK_TIME=0x%08x PHY_DATA_TIME=0x%08x EOTP_EN=0x%08x\n", -+ tag, readl(®->PHY_STATUS), -+ readl(®->PHY_LANE_NUM_CONFIG), -+ readl(®->PHY_CLKLANE_TIME_CONFIG), -+ readl(®->PHY_DATALANE_TIME_CONFIG), -+ readl(®->EOTP_EN)); -+} -+ - #define SPRD_MIPI_DSI_FMT_DSC 0xff - static u32 fmt_to_coding(u32 fmt) - { -@@ -298,7 +323,8 @@ int sprd_dsi_dpi_video(struct sprd_dsi *dsi) - dsi_hal_vblk_cmd_trans_limit(dsi, 0x80); - if (!ctx->hporch_lp_disable) - dsi_hal_dpi_hporch_lp_en(dsi, 1); -- dsi_hal_dpi_vporch_lp_en(dsi, 1); -+ dsi_hal_dpi_hporch_lp_en(dsi, 0); -+ dsi_hal_dpi_vporch_lp_en(dsi, 0); - dsi_hal_dpi_hsync_pol(dsi, 0); - dsi_hal_dpi_vsync_pol(dsi, 0); - dsi_hal_dpi_data_en_pol(dsi, 0); -@@ -319,6 +345,11 @@ int sprd_dsi_dpi_video(struct sprd_dsi *dsi) - dsi_hal_dpi_video_packet_size(dsi, video_size); - dsi_hal_dpi_null_packet_size(dsi, 0); - dsi_hal_dpi_chunk_num(dsi, 0); -+ pr_info("DSI DPI video: burst=%u coding=%u video_size=%u chunks=%u null=%u Bpp_x100=%u ratio_x1000=%u hline=%u hs=%u hbp=%u vact=%u vfp=%u vbp=%u vs=%u hporch_lp_disable=%u\n", -+ ctx->burst_mode, coding, video_size, 0, 0, Bpp_x100, -+ ratio_x1000, hline, vm->hsync_len, vm->hback_porch, -+ vm->vactive, vm->vfront_porch, vm->vback_porch, -+ vm->vsync_len, ctx->hporch_lp_disable); - } else { - /* non burst transmission */ - null_pkt_size = 0; -@@ -326,21 +357,34 @@ int sprd_dsi_dpi_video(struct sprd_dsi *dsi) - /* bytes to be sent - first as one chunk */ - bytes_per_chunk = vm->hactive * Bpp_x100 / 100 + pkt_header; - -- /* hline total bytes from the DPI interface */ -+ /* -+ * hline total bytes from the DPI interface. -+ * ctx->byte_clk is the byte clock for one data lane, so the -+ * available payload budget across the whole DSI link scales -+ * with the number of enabled lanes. -+ */ - total_bytes = (vm->hactive + vm->hfront_porch) * -- ratio_x1000 / ctx->lanes / 1000; -+ ratio_x1000 * ctx->lanes / 1000; -+ pr_info("DSI DPI budget: total=%u chunk=%u lanes=%u byte_clk=%u pclk=%lu ratio=%u hact=%u hfp=%u\n", -+ total_bytes, bytes_per_chunk, ctx->lanes, ctx->byte_clk, -+ vm->pixelclock, ratio_x1000, vm->hactive, -+ vm->hfront_porch); - - /* check if the pixels actually fit on the DSI link */ - if (total_bytes < bytes_per_chunk) { -- pr_err("current resolution can not be set\n"); -+ pr_err("current resolution can not be set: total=%u chunk=%u lanes=%u byte_clk=%u pclk=%lu\n", -+ total_bytes, bytes_per_chunk, ctx->lanes, -+ ctx->byte_clk, vm->pixelclock); -+ dsi_hal_power_en(dsi, 1); -+ sprd_dsi_dump_video_regs(dsi, "dpi-video-budget-fail"); - return -EINVAL; - } - - chunk_overhead = total_bytes - bytes_per_chunk; - -- /* overhead higher than 1 -> enable multi packets */ - if (chunk_overhead > 1) { - -+ /* overhead higher than 1 -> enable multi packets */ - /* multi packets */ - for (video_size = video_size_step; - video_size < vm->hactive; -@@ -383,11 +427,18 @@ int sprd_dsi_dpi_video(struct sprd_dsi *dsi) - dsi_hal_dpi_video_packet_size(dsi, video_size); - dsi_hal_dpi_null_packet_size(dsi, null_pkt_size); - dsi_hal_dpi_chunk_num(dsi, chunks); -+ pr_info("DSI DPI video: burst=%u coding=%u video_size=%u chunks=%u null=%u Bpp_x100=%u ratio_x1000=%u hline=%u hs=%u hbp=%u vact=%u vfp=%u vbp=%u vs=%u hporch_lp_disable=%u\n", -+ ctx->burst_mode, coding, video_size, chunks, -+ null_pkt_size, Bpp_x100, ratio_x1000, hline, -+ vm->hsync_len, vm->hback_porch, vm->vactive, -+ vm->vfront_porch, vm->vback_porch, vm->vsync_len, -+ ctx->hporch_lp_disable); - } - - dsi_hal_int0_mask(dsi, ctx->int0_mask); - dsi_hal_int1_mask(dsi, ctx->int1_mask); - dsi_hal_power_en(dsi, 1); -+ sprd_dsi_dump_video_regs(dsi, "after-dpi-video"); - - return 0; - } -diff --git a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sprd_dsi.c b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sprd_dsi.c -index 85e56d55fe16..5b29adf27337 100644 ---- a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sprd_dsi.c -+++ b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sprd_dsi.c -@@ -25,6 +25,7 @@ - #include "sprd_dsi.h" - #include "sprd_dsi_panel.h" - #include "dsi/sprd_dsi_api.h" -+#include "dsi/sprd_dsi_hal.h" - #include "dphy/sprd_dphy_api.h" - #include "sysfs/sysfs_display.h" - -@@ -37,6 +38,9 @@ - - static void sprd_dsi_enable(struct sprd_dsi *dsi) - { -+ DRM_INFO("sprd_dsi_enable: enter work_mode=%d burst_mode=%d\n", -+ dsi->ctx.work_mode, dsi->ctx.burst_mode); -+ - if (dsi->glb->power) - dsi->glb->power(&dsi->ctx, true); - if (dsi->glb->enable) -@@ -50,6 +54,9 @@ static void sprd_dsi_enable(struct sprd_dsi *dsi) - sprd_dsi_dpi_video(dsi); - else - sprd_dsi_edpi_video(dsi); -+ -+ DRM_INFO("sprd_dsi_enable: exit work_mode=%d burst_mode=%d\n", -+ dsi->ctx.work_mode, dsi->ctx.burst_mode); - } - - static void sprd_dsi_disable(struct sprd_dsi *dsi) -@@ -62,6 +69,38 @@ static void sprd_dsi_disable(struct sprd_dsi *dsi) - dsi->glb->power(&dsi->ctx, false); - } - -+static void sprd_dsi_dump_link_status(struct sprd_dsi *dsi, const char *tag) -+{ -+ DRM_INFO("DSI ctx[%s]: enabled=%d work_mode=%d burst_mode=%d lanes=%d phy_freq=%u byte_clk=%u esc_clk=%u dpi_clk_div=%d nc_clk=%d hporch_lp_disable=%d video_lp_cmd=%d frame_ack=%d phy_enabled=%d ulps_enable=%d\n", -+ tag, dsi->ctx.enabled, dsi->ctx.work_mode, -+ dsi->ctx.burst_mode, dsi->ctx.lanes, -+ dsi->phy ? dsi->phy->ctx.freq : 0, dsi->ctx.byte_clk, -+ dsi->ctx.esc_clk, dsi->ctx.dpi_clk_div, dsi->ctx.nc_clk_en, -+ dsi->ctx.hporch_lp_disable, dsi->ctx.video_lp_cmd_en, -+ dsi->ctx.frame_ack_en, -+ dsi->phy ? dsi->phy->ctx.enabled : 0, -+ dsi->phy ? dsi->phy->ctx.ulps_enable : 0); -+ DRM_INFO("DSI vm[%s]: pclk=%lu h=%u/%u/%u/%u v=%u/%u/%u/%u format=0x%x\n", -+ tag, dsi->ctx.vm.pixelclock, dsi->ctx.vm.hactive, -+ dsi->ctx.vm.hfront_porch, dsi->ctx.vm.hsync_len, -+ dsi->ctx.vm.hback_porch, dsi->ctx.vm.vactive, -+ dsi->ctx.vm.vfront_porch, dsi->ctx.vm.vsync_len, -+ dsi->ctx.vm.vback_porch, dsi->ctx.format); -+} -+ -+static bool sprd_panel_is_lt8912b_dummy(struct sprd_panel *panel) -+{ -+ return panel && panel->lcd_name && -+ !strcmp(panel->lcd_name, "lcd_dummy_mipi_hd"); -+} -+ -+static void sprd_dsi_disable_eotp_for_lt8912b(struct sprd_dsi *dsi) -+{ -+ dsi_hal_eotp_rx_en(dsi, 0); -+ dsi_hal_eotp_tx_en(dsi, 0); -+ DRM_INFO("LT8912B debug: force DSI TX/RX EOTP disabled\n"); -+} -+ - int dsi_panel_set_dpms_mode(struct sprd_dsi *dsi) - { - mutex_lock(&dsi->lock); -@@ -108,10 +147,14 @@ static void sprd_dsi_encoder_enable(struct drm_encoder *encoder) - struct sprd_dsi *dsi = encoder_to_dsi(encoder); - struct sprd_crtc *crtc = to_sprd_crtc(encoder->crtc); - struct sprd_dpu *dpu = crtc->priv; -+ struct sprd_panel *panel = NULL; - - DRM_INFO("%s(last_dpms=%d, dpms=%d)\n", - __func__, dsi->ctx.last_dpms, dsi->ctx.dpms); - -+ if (dsi->panel) -+ panel = container_of(dsi->panel, struct sprd_panel, base); -+ - mutex_lock(&dsi->lock); - /* add if condition to avoid resume dsi for SR feature. - * if esd recovery happened during display suspend, skip dsi resume. -@@ -134,6 +177,33 @@ static void sprd_dsi_encoder_enable(struct drm_encoder *encoder) - - if (dsi->ctx.enabled) { - DRM_INFO("dsi is initialized\n"); -+ sprd_dsi_dump_link_status(dsi, "already-enabled"); -+ if (!strcmp(dpu->ctx.version, "dpu-r6p0") && -+ dsi->ctx.work_mode == DSI_MODE_VIDEO) { -+ if (sprd_panel_is_lt8912b_dummy(panel)) -+ sprd_dsi_disable_eotp_for_lt8912b(dsi); -+ -+ /* -+ * Bootloader marks DSI as enabled, so the normal enable -+ * path is skipped. Do not reset/power-cycle DSI here: -+ * some bootloader handoff states lock up if we run the -+ * full enable path again. Just refresh the DPI video -+ * registers and make sure HS clock/video mode are selected. -+ */ -+ DRM_INFO("DSI already enabled, refresh DPI video path\n"); -+ sprd_dsi_dpi_video(dsi); -+ sprd_dsi_set_work_mode(dsi, dsi->ctx.work_mode); -+ sprd_dsi_state_reset(dsi); -+ if (dsi->ctx.nc_clk_en) -+ sprd_dsi_nc_clk_en(dsi, true); -+ else -+ sprd_dphy_hs_clk_en(dsi->phy, true); -+ if (!dpu->ctx.enabled) -+ sprd_dpu_resume(dpu); -+ dpu->ctx.stopped = true; -+ sprd_dpu_run(crtc->priv); -+ sprd_dsi_dump_link_status(dsi, "already-refresh"); -+ } - mutex_unlock(&dsi->lock); - return; - } -@@ -144,6 +214,9 @@ static void sprd_dsi_encoder_enable(struct drm_encoder *encoder) - sprd_dsi_enable(dsi); - sprd_dphy_enable(dsi->phy); - -+ if (sprd_panel_is_lt8912b_dummy(panel)) -+ sprd_dsi_disable_eotp_for_lt8912b(dsi); -+ - sprd_dsi_lp_cmd_enable(dsi, true); - - if (dsi->panel) { -@@ -167,6 +240,13 @@ static void sprd_dsi_encoder_enable(struct drm_encoder *encoder) - sprd_dsi_set_work_mode(dsi, dsi->ctx.work_mode); - sprd_dsi_state_reset(dsi); - -+ if (dsi->ctx.work_mode == DSI_MODE_VIDEO) { -+ DRM_INFO("DSI normal enable, refresh DPI video after mode set\n"); -+ sprd_dsi_dpi_video(dsi); -+ sprd_dsi_set_work_mode(dsi, dsi->ctx.work_mode); -+ sprd_dsi_state_reset(dsi); -+ } -+ - if ((dsi->ctx.work_mode == DSI_MODE_VIDEO) - && dsi->ctx.video_lp_cmd_en) - sprd_dsi_lp_cmd_enable(dsi, true); -@@ -200,6 +280,8 @@ static void sprd_dsi_encoder_enable(struct drm_encoder *encoder) - if (dsi->ctx.last_dpms != DRM_MODE_DPMS_SUSPEND) - sprd_dpu_run(crtc->priv); - -+ sprd_dsi_dump_link_status(dsi, "after-enable"); -+ - dsi->ctx.enabled = true; - dsi->ctx.last_dpms = dsi->ctx.dpms; - -diff --git a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sysfs/sysfs_dphy.c b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sysfs/sysfs_dphy.c -index f375be867e4a..b05c93de00f1 100644 ---- a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sysfs/sysfs_dphy.c -+++ b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sysfs/sysfs_dphy.c -@@ -175,6 +175,8 @@ static ssize_t ssc_store(struct device *dev, - struct sprd_dphy *dphy = dev_get_drvdata(dev); - int ret; - -+ return count; -+ - mutex_lock(&dphy->ctx.lock); - if (!dphy->ctx.enabled) { - mutex_unlock(&dphy->ctx.lock); -@@ -215,6 +217,8 @@ static ssize_t hop_store(struct device *dev, - int ret; - int delta; - -+ return count; -+ - mutex_lock(&dphy->ctx.lock); - if (!dphy->ctx.enabled) { - mutex_unlock(&dphy->ctx.lock); -diff --git a/source/kernel/kernel5.4/drivers/video/Kconfig b/source/kernel/kernel5.4/drivers/video/Kconfig -index 427a993c7f57..2ae4f7e67db3 100644 ---- a/source/kernel/kernel5.4/drivers/video/Kconfig -+++ b/source/kernel/kernel5.4/drivers/video/Kconfig -@@ -25,6 +25,8 @@ endmenu - - source "drivers/video/backlight/Kconfig" - -+source "drivers/video/LT8912B/Kconfig" -+ - config VGASTATE - tristate - default n -diff --git a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -new file mode 100644 ---- a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -0,0 +1,54 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * LT8912B MIPI-DSI to HDMI 1080p dummy panel config. -+ */ -+ -+/ { -+ fragment { -+ target-path = "/"; -+ __overlay__ { -+ lcds { -+ lcd_dummy_mipi_hd: lcd_dummy_mipi_hd { -+ sprd,dsi-work-mode = <2>; /* video pulse mode */ -+ sprd,dsi-lane-number = <4>; -+ sprd,dsi-color-format = "rgb888"; -+ -+ sprd,phy-bit-clock = <1200000>; /* kbps 921600 1200000 */ -+ sprd,phy-escape-clock = <20000>; /* kHz */ -+ sprd,video-lp-cmd-enable = <0>; -+ sprd,hporch-lp-disable = <1>; -+ sprd,width-mm = <121>; -+ sprd,height-mm = <68>; -+ sprd,esd-check-enable = <0>; -+ sprd,esd-check-mode = <1>; -+ sprd,esd-check-period = <1000>; -+ sprd,panel-if-type = <2>; -+ sprd,reset-on-sequence = <1 5>, <0 5>, <1 5>, <0 5>, <1 20>; -+ sprd,reset-off-sequence = <0 20>; -+ sprd,initial-command = [ -+ ]; -+ sprd,sleep-in-command = [ -+ ]; -+ sprd,sleep-out-command = [ -+ ]; -+ -+ display-timings { -+ native-mode = <<8912b_1080p_timing0>; -+ -+ lt8912b_1080p_timing0: timing0 { -+ clock-frequency = <153600000>; -+ hactive = <1920>; -+ vactive = <1080>; -+ hfront-porch = <88>; -+ hsync-len = <44>; -+ hback-porch = <148>; -+ vfront-porch = <56>; -+ vsync-len = <6>; -+ vback-porch = <60>; -+ }; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/Kconfig b/source/kernel/kernel5.4/drivers/video/LT8912B/Kconfig -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/Kconfig -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/Kconfig -@@ -0,0 +1,9 @@ -+ -+config LT8912B -+ tristate "LT8912B Driver" -+ default n -+ help -+ Control LT8912B Chip -+ Select m:build as a separate module; -+ Select y:Build into the kernel -+ Select n:Not build -\ No newline at end of file -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/Makefile b/source/kernel/kernel5.4/drivers/video/LT8912B/Makefile -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/Makefile -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/Makefile -@@ -0,0 +1,4 @@ -+ -+lt8912b-y := src/LontiumDrv.o src/LT8912B_Main.o src/LT8912B.o src/OcmI2cMaster.o \ -+ -+obj-$(CONFIG_LT8912B) += lt8912b.o -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B.h b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B.h -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B.h -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B.h -@@ -0,0 +1,72 @@ -+ -+#ifndef _LT8912B_H -+#define _LT8912B_H -+ -+#define _1080P_60Hz -+ -+/* output mode */ -+#define _hdmi_output -+#define _lvds_bypass -+ -+//#define _pattern_test_ -+ -+//#define _lane_swap_ //mipi input 3210 -+//#define _pn_swap_ //mipi input lane pn swap -+ -+#define dds_debug -+ -+/* lanes */ -+#define lane_cnt 0 /*0: 4lane; 1: 1lane; 2: 2lane; 3: 3lane;*/ -+ -+ -+typedef struct video_timing{ -+u16 hfp; -+u16 hs; -+u16 hbp; -+u16 hact; -+u16 htotal; -+u16 vfp; -+u16 vs; -+u16 vbp; -+u16 vact; -+u16 vtotal; -+bool h_polarity; -+bool v_polarity; -+u16 vic; -+u8 aspact_ratio; // 0=no data, 1=4:3, 2=16:9, 3=no data. -+u32 pclk_khz; -+}_video_timing; -+ -+typedef enum -+{ -+ I2S_2CH, -+ I2S_8CH, -+ SPDIF -+}_Audio_Input_Mode; -+ -+#define Audio_Input_Mode I2S_2CH -+ -+#define AR_ND 0x00 -+#define AR_4_3 0x01 -+#define AR_16_9 0x02 -+ -+typedef struct panel_parameter -+{ -+ u16 hfp; -+ u16 hs; -+ u16 hbp; -+ u16 hact; -+ u16 htotal; -+ u16 vfp; -+ u16 vs; -+ u16 vbp; -+ u16 vact; -+ u16 vtotal; -+ u32 pclk_khz; -+}_panel_parameter; -+ -+extern void LT8912B_Config(void); -+ -+extern u8 Tx_HPD; -+ -+#endif -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B_Main.h b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B_Main.h -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B_Main.h -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B_Main.h -@@ -0,0 +1,5 @@ -+#ifndef _LT8912B_MAIN_H_ -+#define _LT8912B_MAIN_H_ -+ -+extern int LT8912B_Main(void *data); -+#endif -\ No newline at end of file -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LontiumDrv.h b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LontiumDrv.h -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LontiumDrv.h -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LontiumDrv.h -@@ -0,0 +1,39 @@ -+#ifndef _LONTIUMDRV_H_ -+#define _LONTIUMDRV_H_ -+ -+ -+struct _lt8912b{ -+ struct device *dev; -+ struct mutex ocm_lock; -+ struct gpio_desc *reset_gpio; -+ struct gpio_desc *power_gpio; -+ struct i2c_client *i2c_stu; -+ struct regmap *chip_regmap; -+ struct addr_1{ -+ struct i2c_client *i2c_stu; -+ struct regmap *regmap; -+ }*addr_1; -+ struct addr_2{ -+ struct i2c_client *i2c_stu; -+ struct regmap *regmap; -+ }*addr_2; -+ -+}; -+ -+ -+ -+typedef struct -+{ -+ u8 address; -+ u8 value; -+} Chip_Control_Args; -+ -+ -+extern struct _lt8912b *lt8912b; -+extern volatile bool Main_Loop; -+extern const char *LOG_FLAG; -+ -+extern u8 addr_1; -+extern u8 addr_2; -+ -+#endif -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/include/OcmI2cMaster.h b/source/kernel/kernel5.4/drivers/video/LT8912B/include/OcmI2cMaster.h -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/include/OcmI2cMaster.h -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/include/OcmI2cMaster.h -@@ -0,0 +1,10 @@ -+#ifndef _OCMI2CMASTER_H_ -+#define _OCMI2CMASTER_H_ -+ -+ -+extern int HDMI_WriteI2C_Byte(u8 addr,u8 data); -+extern int HDMI_ReadI2C_Byte(u8 addr); -+ -+extern u8 I2CADR; -+ -+#endif -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/include/include.h b/source/kernel/kernel5.4/drivers/video/LT8912B/include/include.h -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/include/include.h -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/include/include.h -@@ -0,0 +1,41 @@ -+#ifndef _INCLUDE_H_ -+#define _INCLUDE_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+ -+#include "LontiumDrv.h" -+ -+#include "LT8912B_Main.h" -+#include "LT8912B.h" -+ -+ -+#include "OcmI2cMaster.h" -+ -+ -+ -+ -+#endif -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c -@@ -0,0 +1,790 @@ -+ -+#include "../include/include.h" -+ -+u8 Hsync_H_last = 0x00; -+u8 Hsync_L_last = 0x00; -+u8 Vsync_H_last = 0x00; -+u8 Vsync_L_last = 0x00; -+ -+u8 Hsync_L, Hsync_H, Vsync_L, Vsync_H; -+u8 mipi_det_fail_count = 0; -+u8 mipi_relock_count = 0; -+ -+ -+bool suspend_on = 0; -+ -+u8 Tx_HPD=0; -+ -+// hfp, hs, hbp, hact, htotal, vfp, vs, vbp, vact, vtotal, hfp, hs, hbp, hact, htotal, vfp, vs, vbp, vact, vtotal, h_polary, v_polary, vic, aspact_ratio, pclk_khz -+struct video_timing video_640x480_60Hz = {16, 96, 48, 640, 800, 10, 2, 33, 480, 525, 0,0, 1, AR_4_3, 25000}; -+struct video_timing video_720x480_60Hz = {16, 62, 60, 720, 858, 9, 6, 30, 480, 525, 0,0, 2, AR_4_3, 27000}; -+struct video_timing video_720x576_50Hz = {12, 64, 68, 720, 864, 5, 5, 39, 576, 625, 0,0,17, AR_4_3, 27000}; -+struct video_timing video_800x600_60Hz = {48, 128, 88, 800, 1056, 1, 4, 23, 600, 628, 1,1, 0, AR_16_9, 40000}; -+struct video_timing video_1024x768_60Hz = {24, 136, 160, 1024, 1344, 3, 6, 29, 768, 806, 0,0, 0, AR_16_9, 65000}; -+struct video_timing video_1280x720_60Hz = {110, 40, 220, 1280, 1650, 5, 5, 20, 720, 750, 1,1, 4, AR_16_9, 74250}; -+struct video_timing video_1280x800_60Hz = {28, 32, 100, 1280, 1440, 2, 6, 15, 800, 823, 0,0, 0, AR_16_9, 71000}; -+//struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 4, 5, 36, 1080, 1125, 1,1,16, AR_16_9, 148500}; -+struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 56, 6, 60, 1080, 1202, 1,1, 0, AR_16_9, 153600}; -+ -+struct video_timing *video; -+ -+void DDSConfig(void); -+ -+void DigitalClockEn(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x02,0xf7); -+ HDMI_WriteI2C_Byte(0x08,0xff); -+ HDMI_WriteI2C_Byte(0x09,0xff); -+ HDMI_WriteI2C_Byte(0x0a,0xff); -+ HDMI_WriteI2C_Byte(0x0b,0x7c); -+ HDMI_WriteI2C_Byte(0x0c,0xff); -+} -+void TxAnalog(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x31,0xE1); -+ HDMI_WriteI2C_Byte(0x32,0xE1); -+ HDMI_WriteI2C_Byte(0x33,0x0c); //en/disable hdmid output -+ HDMI_WriteI2C_Byte(0x37,0x00); -+ HDMI_WriteI2C_Byte(0x38,0x22); -+ HDMI_WriteI2C_Byte(0x60,0x82); -+} -+ -+void CbusAnalog(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x39,0x45); -+ HDMI_WriteI2C_Byte(0x3a,0x00); //20180719 -+ HDMI_WriteI2C_Byte(0x3b,0x00); -+} -+ -+void HDMIPllAnalog(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x44,0x31); -+ HDMI_WriteI2C_Byte(0x55,0x44); -+ HDMI_WriteI2C_Byte(0x57,0x01); -+ HDMI_WriteI2C_Byte(0x5a,0x02); -+} -+ -+void AviInfoframe(struct video_timing *video_format) -+{ -+ u8 VIC = video_format->vic; -+ u8 AR = video_format->aspact_ratio; -+ u8 pb0,pb2,pb4,Sync_Polarity; -+ -+ I2CADR = 0x94; -+ HDMI_WriteI2C_Byte(0x3c,0x41); //enable null package -+ -+ Sync_Polarity = (video_format->h_polarity*0x02) + (video_format->v_polarity*0x01); -+ pb2 = (AR<<4) + 0x08; -+ pb4 = VIC; -+ pb0 = (((pb2 + pb4) <= 0x5f)?(0x5f - pb2 - pb4):(0x15f - pb2 - pb4)); -+ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0xab,Sync_Polarity); //sync polarity -+ -+ I2CADR = 0x94; -+ HDMI_WriteI2C_Byte(0x43,pb0); //PB0:check sum -+ HDMI_WriteI2C_Byte(0x44,0x10); //PB1:RGB888 -+ HDMI_WriteI2C_Byte(0x45,pb2); //PB2 -+ HDMI_WriteI2C_Byte(0x46,0x00); //PB3 -+ HDMI_WriteI2C_Byte(0x47,pb4); //PB4:vic -+} -+ -+void MipiAnalog(void) -+{ -+ I2CADR = 0x90; -+ #ifdef _pn_swap_ -+ HDMI_WriteI2C_Byte(0x3e,0xf6); //P/N swap -+ #else -+ HDMI_WriteI2C_Byte(0x3e,0xd6); //if mipi pin map follow reference design, no need swap P/N. -+ #endif -+ -+ HDMI_WriteI2C_Byte(0x3f,0xd4);//EQ -+ HDMI_WriteI2C_Byte(0x41,0x3c);//EQ -+} -+ -+void MipiBasicSet(void) -+{ -+ I2CADR = 0x92; -+ HDMI_WriteI2C_Byte(0x10,0x01); // term en -+ HDMI_WriteI2C_Byte(0x11,0x10); // settle -+ //HDMI_WriteI2C_Byte(0x12,0x08); // trail -+ HDMI_WriteI2C_Byte(0x13,lane_cnt); //00 4 lane //01 1 lane //02 2 lane //03 3lane -+ HDMI_WriteI2C_Byte(0x14,0x00); //debug mux -+ -+ #ifdef _lane_swap_ //for EVB only, if mipi pin map follow reference design, no need swap lane. -+ HDMI_WriteI2C_Byte(0x15,0xa8); //lane swap:3210 -+ printk("%s nmipi basic set: lane swap 3210, %d\n",LOG_FLAG,lane_cnt); -+ #else -+ HDMI_WriteI2C_Byte(0x15,0x00); //lane swap:0123 -+ #endif -+ -+ HDMI_WriteI2C_Byte(0x1a,0x03); // hshift 3 -+ HDMI_WriteI2C_Byte(0x1b,0x03); // vshift 3 -+} -+ -+void MIPI_Video_Setup(struct video_timing *video_format) -+{ -+ I2CADR = 0x92; -+ HDMI_WriteI2C_Byte(0x18,(u8)(video_format->hs%256)); // hwidth -+ HDMI_WriteI2C_Byte(0x19,(u8)(video_format->vs%256)); // vwidth -+ HDMI_WriteI2C_Byte(0x1c,(u8)(video_format->hact%256)); // H_active[7:0] -+ HDMI_WriteI2C_Byte(0x1d,(u8)(video_format->hact/256)); // H_active[15:8] -+ HDMI_WriteI2C_Byte(0x2f,0x0c); // fifo_buff_length 12 -+ HDMI_WriteI2C_Byte(0x34,(u8)(video_format->htotal%256)); // H_total[7:0] -+ HDMI_WriteI2C_Byte(0x35,(u8)(video_format->htotal/256)); // H_total[15:8] -+ HDMI_WriteI2C_Byte(0x36,(u8)(video_format->vtotal%256)); // V_total[7:0] -+ HDMI_WriteI2C_Byte(0x37,(u8)(video_format->vtotal/256)); // V_total[15:8] -+ HDMI_WriteI2C_Byte(0x38,(u8)(video_format->vbp%256)); // VBP[7:0] -+ HDMI_WriteI2C_Byte(0x39,(u8)(video_format->vbp/256)); // VBP[15:8] -+ HDMI_WriteI2C_Byte(0x3a,(u8)(video_format->vfp%256)); // VFP[7:0] -+ HDMI_WriteI2C_Byte(0x3b,(u8)(video_format->vfp/256)); // VFP[15:8] -+ HDMI_WriteI2C_Byte(0x3c,(u8)(video_format->hbp%256)); // HBP[7:0] -+ HDMI_WriteI2C_Byte(0x3d,(u8)(video_format->hbp/256)); // HBP[15:8] -+ HDMI_WriteI2C_Byte(0x3e,(u8)(video_format->hfp%256)); // HFP[7:0] -+ HDMI_WriteI2C_Byte(0x3f,(u8)(video_format->hfp/256)); // HFP[15:8] -+ video = video_format; -+} -+ -+void MIPIRxLogicRes(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x03,0x7f); //mipi rx reset -+ msleep(10); -+ HDMI_WriteI2C_Byte(0x03,0xff); -+ -+ HDMI_WriteI2C_Byte(0x05,0xfb); //dds reset -+ msleep(10); -+ HDMI_WriteI2C_Byte(0x05,0xff); -+} -+ -+void LT8912B_MIPI_Relock(void) -+{ -+ printk("%s relock MIPI RX after detect timeout, retry=%u\n", -+ LOG_FLAG, mipi_relock_count); -+ -+ MipiAnalog(); -+ MipiBasicSet(); -+ DDSConfig(); -+ MIPI_Video_Setup(&video_1920x1080_60Hz); -+ AviInfoframe(&video_1920x1080_60Hz); -+ MIPIRxLogicRes(); -+} -+ -+void DDSConfig(void) -+{ -+ I2CADR = 0x92; -+ HDMI_WriteI2C_Byte(0x4e,0x93);//strm_sw_freq_word[ 7: 0] -+ HDMI_WriteI2C_Byte(0x4f,0x3E);//strm_sw_freq_word[15: 8] -+ HDMI_WriteI2C_Byte(0x50,0x29);//strm_sw_freq_word[23:16] -+ HDMI_WriteI2C_Byte(0x51,0x80);//[0]=strm_sw_freq_word[24] -+ HDMI_WriteI2C_Byte(0x1e,0x4f); -+ HDMI_WriteI2C_Byte(0x1f,0x5e);//full_value 464 -+ HDMI_WriteI2C_Byte(0x20,0x01); -+ HDMI_WriteI2C_Byte(0x21,0x2c);//full_value1 416 -+ HDMI_WriteI2C_Byte(0x22,0x01); -+ HDMI_WriteI2C_Byte(0x23,0xfa);//full_value2 400 -+ HDMI_WriteI2C_Byte(0x24,0x00); -+ HDMI_WriteI2C_Byte(0x25,0xc8);//full_value3 384 -+ HDMI_WriteI2C_Byte(0x26,0x00); -+ HDMI_WriteI2C_Byte(0x27,0x5e);//empty_value 464 -+ HDMI_WriteI2C_Byte(0x28,0x01); -+ HDMI_WriteI2C_Byte(0x29,0x2c);//empty_value1 416 -+ HDMI_WriteI2C_Byte(0x2a,0x01); -+ HDMI_WriteI2C_Byte(0x2b,0xfa);//empty_value2 400 -+ HDMI_WriteI2C_Byte(0x2c,0x00); -+ HDMI_WriteI2C_Byte(0x2d,0xc8);//empty_value3 384 -+ HDMI_WriteI2C_Byte(0x2e,0x00); -+ HDMI_WriteI2C_Byte(0x42,0x64);//tmr_set[ 7:0]:100us -+ HDMI_WriteI2C_Byte(0x43,0x00);//tmr_set[15:8]:100us -+ HDMI_WriteI2C_Byte(0x44,0x04);//timer step -+ HDMI_WriteI2C_Byte(0x45,0x00); -+ HDMI_WriteI2C_Byte(0x46,0x59); -+ HDMI_WriteI2C_Byte(0x47,0x00); -+ HDMI_WriteI2C_Byte(0x48,0xf2); -+ HDMI_WriteI2C_Byte(0x49,0x06); -+ HDMI_WriteI2C_Byte(0x4a,0x00); -+ HDMI_WriteI2C_Byte(0x4b,0x72); -+ HDMI_WriteI2C_Byte(0x4c,0x45); -+ HDMI_WriteI2C_Byte(0x4d,0x00); -+ HDMI_WriteI2C_Byte(0x52,0x08);// trend step -+ HDMI_WriteI2C_Byte(0x53,0x00); -+ HDMI_WriteI2C_Byte(0x54,0xb2); -+ HDMI_WriteI2C_Byte(0x55,0x00); -+ HDMI_WriteI2C_Byte(0x56,0xe4); -+ HDMI_WriteI2C_Byte(0x57,0x0d); -+ HDMI_WriteI2C_Byte(0x58,0x00); -+ HDMI_WriteI2C_Byte(0x59,0xe4); -+ HDMI_WriteI2C_Byte(0x5a,0x8a); -+ HDMI_WriteI2C_Byte(0x5b,0x00); -+ HDMI_WriteI2C_Byte(0x5c,0x34); -+ HDMI_WriteI2C_Byte(0x51,0x00); -+} -+ -+void AudioIIsEn(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0xB2,0x01);//DVI mode:0x00; HDMI mode:0x01; -+ I2CADR = 0x94; -+ HDMI_WriteI2C_Byte(0x06,0x08); -+ HDMI_WriteI2C_Byte(0x07,0xF0); -+ HDMI_WriteI2C_Byte(0x34,0xD2);//0xE2:32FS; 0xD2:64FS -+ HDMI_WriteI2C_Byte(0x0F,0x2B); -+} -+ -+void AudioSpdifEn(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0xB2,0x01); -+ I2CADR = 0x94; -+ HDMI_WriteI2C_Byte(0x06,0x0e); -+ HDMI_WriteI2C_Byte(0x07,0x00); -+ HDMI_WriteI2C_Byte(0x34,0xD2);//0xE2:32FS; 0xD2:64FS -+} -+ -+void Core_Pll_setup(struct panel_parameter *panel) -+{ -+ u8 cpll_m, cpll_k1,cpll_k2; //cpll_k3; -+ u32 temp; -+ -+ temp=(panel->pclk_khz*7)/25; -+ cpll_m=temp/1000; -+ -+ temp=(panel->pclk_khz*7)/25; -+ temp=temp%1000; -+ //temp=temp*16.384; -+ temp=temp*16384/1000; -+ -+ cpll_k1=temp%256; -+ cpll_k2=temp/256; -+ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x50,0x24);//cp=50uA -+ HDMI_WriteI2C_Byte(0x51,0x05);//xtal_clk as reference,second order passive LPF PLL -+ HDMI_WriteI2C_Byte(0x52,0x14);//use second-order PLL -+ HDMI_WriteI2C_Byte(0x69,cpll_m);//CP_PRESET_DIV_RATIO -+ HDMI_WriteI2C_Byte(0x69,(cpll_m|0x80)); -+ HDMI_WriteI2C_Byte(0x6c,(cpll_k2|0x80));//RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8] -+ HDMI_WriteI2C_Byte(0x6b,cpll_k1); -+ -+ HDMI_WriteI2C_Byte(0x04,0xfb);//core pll reset -+ HDMI_WriteI2C_Byte(0x04,0xff); -+} -+ -+void Core_Pll_bypass(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x50,0x24); //cp=50uA -+ HDMI_WriteI2C_Byte(0x51,0x2d); //Pix_clk as reference,second order passive LPF PLL -+ HDMI_WriteI2C_Byte(0x52,0x04); //loopdiv=0;use second-order PLL -+ HDMI_WriteI2C_Byte(0x69,0x0e); //CP_PRESET_DIV_RATIO -+ HDMI_WriteI2C_Byte(0x69,0x8e); -+ HDMI_WriteI2C_Byte(0x6a,0x00); -+ HDMI_WriteI2C_Byte(0x6c,0xb8); //RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8] -+ HDMI_WriteI2C_Byte(0x6b,0x51); -+ -+ HDMI_WriteI2C_Byte(0x04,0xfb); //core pll reset -+ HDMI_WriteI2C_Byte(0x04,0xff); -+} -+ -+void Lvds_Pll_Reset(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x02,0xf7); //lvds pll reset -+ HDMI_WriteI2C_Byte(0x02,0xff); -+} -+ -+ -+void Scaler_bypass(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x7f,0x00);//disable scaler -+ HDMI_WriteI2C_Byte(0xa8,0x13); -+} -+ -+void Scaler_setup(struct video_timing *input_video,struct panel_parameter *panel) -+{ -+ //for example: 720P to 1280x800 -+ //These register base on MIPI resolution and LVDS panel resolution. -+ u32 h_ratio,v_ratio; -+ u8 i; -+ u32 htotal; -+// h_ratio = input_video->hact*4096.00/panel->hact; -+// v_ratio = input_video->vact*4096.00/panel->vact; -+ h_ratio = input_video->hact*4096/panel->hact; -+ v_ratio = input_video->vact*4096/panel->vact; -+ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x80,0x00); -+ HDMI_WriteI2C_Byte(0x81,0xff); -+ HDMI_WriteI2C_Byte(0x82,0x03); -+ HDMI_WriteI2C_Byte(0x83,(u8)(input_video->hact%256)); -+ HDMI_WriteI2C_Byte(0x84,(u8)(input_video->hact/256)); -+ HDMI_WriteI2C_Byte(0x85,0x80); -+ HDMI_WriteI2C_Byte(0x86,0x10); -+ HDMI_WriteI2C_Byte(0x87,(u8)(panel->htotal%256)); -+ HDMI_WriteI2C_Byte(0x88,(u8)(panel->htotal/256)); -+ HDMI_WriteI2C_Byte(0x89,(u8)(panel->hs%256)); -+ HDMI_WriteI2C_Byte(0x8a,(u8)(panel->hbp%256)); -+ HDMI_WriteI2C_Byte(0x8b,(u8)(panel->vs%256)); -+ HDMI_WriteI2C_Byte(0x8c,(u8)(panel->hact%256)); -+ HDMI_WriteI2C_Byte(0x8d,(u8)(panel->vact%256)); -+ HDMI_WriteI2C_Byte(0x8e,(u8)(panel->vact/256)*16+(panel->hact/256)); -+ HDMI_WriteI2C_Byte(0x8f,(u8)(h_ratio%256)); -+ HDMI_WriteI2C_Byte(0x90,(u8)(h_ratio/256)); -+ HDMI_WriteI2C_Byte(0x91,(u8)(v_ratio%256)); -+ HDMI_WriteI2C_Byte(0x92,(u8)(v_ratio/256)); -+ HDMI_WriteI2C_Byte(0x7f,0x96); -+ //HDMI_WriteI2C_Byte(0x7f,0xb0); -+ //HDMI_WriteI2C_Byte(0xa8,0x3b); -+ HDMI_WriteI2C_Byte(0xa8,0x13); -+ -+ HDMI_WriteI2C_Byte(0x02,0xf7);//lvds pll reset -+ HDMI_WriteI2C_Byte(0x02,0xff); -+ -+ HDMI_WriteI2C_Byte(0x03,0xcf);//scaler reset -+ HDMI_WriteI2C_Byte(0x03,0xff); -+ -+ HDMI_WriteI2C_Byte(0x7f,0xb0); -+ -+ for(i = 0; i < 300; i++) -+ { -+ if(HDMI_ReadI2C_Byte(0xa7)&0x20) -+ { -+ htotal = (HDMI_ReadI2C_Byte(0xa7)&0x0f)*0x100 + HDMI_ReadI2C_Byte(0xa6); -+ printk("%s scaler setup htotal = %d.\n",LOG_FLAG,htotal); -+ -+ break; -+ //please set "htotal" to panel_parameter's htotal. -+ } -+ printk("%s scaler loop = %d\n",LOG_FLAG, i); -+ msleep(100); -+ } -+} -+void LvdsPowerUp(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x44,0x30); -+ HDMI_WriteI2C_Byte(0x51,0x05); -+} -+void LvdsPowerDown(void) -+{ -+ I2CADR = 0x90; -+ //HDMI_WriteI2C_Byte(0x44,0x31); -+ HDMI_WriteI2C_Byte(0x51,0x15); // -+ //HDMI_WriteI2C_Byte(0x03,0xfb); -+} -+ -+void LvdsBypass(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x50,0x24); //cp=50uA -+ HDMI_WriteI2C_Byte(0x51,0x2d); //Pix_clk as reference,second order passive LPF PLL -+ HDMI_WriteI2C_Byte(0x52,0x04); //loopdiv=0;use second-order PLL -+ HDMI_WriteI2C_Byte(0x69,0x0e); //CP_PRESET_DIV_RATIO -+ HDMI_WriteI2C_Byte(0x69,0x8e); -+ HDMI_WriteI2C_Byte(0x6a,0x00); -+ HDMI_WriteI2C_Byte(0x6c,0xb8); //RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8] -+ HDMI_WriteI2C_Byte(0x6b,0x51); -+ -+ HDMI_WriteI2C_Byte(0x04,0xfb); //core pll reset -+ HDMI_WriteI2C_Byte(0x04,0xff); -+ -+ HDMI_WriteI2C_Byte(0x7f,0x00); //disable scaler -+ HDMI_WriteI2C_Byte(0xa8,0x13); //0x13:VSEA ; 0x33:JEIDA; -+} -+ -+void LvdsOutput(bool on) -+{ -+ if(on) -+ { -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x02,0xf7); //lvds pll reset -+ HDMI_WriteI2C_Byte(0x02,0xff); //scaler module reset -+ HDMI_WriteI2C_Byte(0x03,0xcb); //lvds tx module reset -+ HDMI_WriteI2C_Byte(0x03,0xfb); -+ HDMI_WriteI2C_Byte(0x03,0xff); -+ HDMI_WriteI2C_Byte(0x44,0x30); //enbale lvds output -+ printk("%s LT8912_lvds_output_enable!\n",LOG_FLAG); -+ -+ }else{ -+ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x44,0x31); -+ } -+} -+ -+ -+void HdmiOutput(bool on) -+{ -+ if(on) -+ { -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x33,0x0e); //enable hdmi output -+ printk("%s HDMI output Enable.\n",LOG_FLAG); -+ } -+ else -+ { -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x33,0x0c); //disable hdmi output -+ printk("%s HDMI output Disable.\n",LOG_FLAG); -+ } -+} -+ -+ -+void LvdsScalerResult(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x7f,0xb0); -+} -+ -+ -+void ScalerReset(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x03,0xcf); -+ HDMI_WriteI2C_Byte(0x03,0xff); -+} -+ -+ -+void lt8912_check_dds(void) -+{ -+ u8 reg_920c, reg_920d, reg_920e, reg_920f; -+ u8 i; -+ for(i = 0; i < 10; i++) -+ { -+ I2CADR = 0x92; -+ reg_920c = HDMI_ReadI2C_Byte(0x0c); -+ reg_920d = HDMI_ReadI2C_Byte(0x0d); -+ reg_920e = HDMI_ReadI2C_Byte(0x0e); -+ reg_920f = HDMI_ReadI2C_Byte(0x0f); -+ printk("%s 0x0c~0f = %02x, %02x, %02x\n",LOG_FLAG,reg_920c, reg_920d, reg_920e); -+// if((reg_920e == 0xd2)&&(reg_920d < 0xff)&&(reg_920d > 0xd0)) //shall update threshold here base on actual dds result. -+// { -+// printk("%s lvds_check_dds: stable!\n",LOG_FLAG); -+// break; -+// } -+ -+ msleep(500); -+ } -+} -+ -+void lvds_output_cfg(void) -+{ -+ LvdsPowerUp(); -+ #ifdef _lvds_bypass -+ LvdsBypass(); -+ #else -+ //Core_Pll_setup(&AA070M0C1); -+ Core_Pll_setup(&KD101FM_1_C001A); -+ Scaler_setup(&video_1280x720_60Hz,&KD101FM_1_C001A); -+ #endif -+} -+ -+void MIPI_Input_det(void) -+{ -+ bool video_valid = false; -+ -+ I2CADR = 0x90; -+ Hsync_L = HDMI_ReadI2C_Byte(0x9c); -+ Hsync_H = HDMI_ReadI2C_Byte(0x9d); -+ Vsync_L = HDMI_ReadI2C_Byte(0x9e); -+ Vsync_H = HDMI_ReadI2C_Byte(0x9f); -+ printk("%s 0x9c~9f = %x, %x, %x, %x.\n", LOG_FLAG,Hsync_H, Hsync_L,Vsync_H, Vsync_L); -+ -+ if (Hsync_H == 0xff && Hsync_L == 0xff && -+ Vsync_H == 0x00 && Vsync_L == 0x00) { -+ if (mipi_det_fail_count < 0xff) -+ mipi_det_fail_count++; -+ -+ if (mipi_det_fail_count >= 10 && mipi_relock_count < 5) { -+ mipi_relock_count++; -+ mipi_det_fail_count = 0; -+ LT8912B_MIPI_Relock(); -+ } -+ } else { -+ mipi_det_fail_count = 0; -+ } -+ -+ if((Hsync_H!=Hsync_H_last)||(Vsync_H!=Vsync_H_last)) /*hiht byte changed*/ -+ { -+ printk("%s 0x9c~9f = %x, %x, %x, %x.\n", LOG_FLAG,Hsync_H, Hsync_L,Vsync_H, Vsync_L); -+ -+ if(Vsync_H==0x02 && Vsync_L <= 0xef&&Vsync_L >= 0xec)//0x2EE -+ { -+ video = &video_1280x720_60Hz; -+ video_valid = true; -+ printk("%s videoformat = VESA_1280x720_60\n",LOG_FLAG); -+ } -+ else if(Vsync_H == 0x03 && Vsync_L <= 0x3a &&Vsync_L >= 0x34)//0x337 -+ { -+ video = &video_1280x800_60Hz; -+ video_valid = true; -+ printk("%s videoformat = VESA_1280x800_60\n",LOG_FLAG); -+ } -+ else if(Vsync_H == 0x04 && Vsync_L <= 0xb6&&Vsync_L >= 0x63)//0x4b2 -+ { -+ video = &video_1920x1080_60Hz; -+ video_valid = true; -+ printk("%s videoformat = 1920x1080_153M6\n",LOG_FLAG); -+ } -+ else -+ { -+ printk("%s videoformat = video_none\n",LOG_FLAG); -+ } -+ -+ Hsync_L_last = Hsync_L; -+ Hsync_H_last = Hsync_H; -+ Vsync_L_last = Vsync_L; -+ Vsync_H_last = Vsync_H; -+ -+ if (video_valid) { -+ mipi_det_fail_count = 0; -+ mipi_relock_count = 0; -+ MIPI_Video_Setup(video); -+ AviInfoframe(video); -+ MIPIRxLogicRes(); -+ } -+ } -+ -+} -+ -+ -+//void dds_clock_debug(void) -+//{ -+// #ifdef dds_debug -+// u8 reg_920c, reg_920d, reg_920e, reg_920f; -+// -+// while(1) -+// { -+// I2CADR = 0x92; -+// reg_920c = HDMI_ReadI2C_Byte(0x0c); -+// reg_920d = HDMI_ReadI2C_Byte(0x0d); -+// reg_920e = HDMI_ReadI2C_Byte(0x0e); -+// reg_920f = HDMI_ReadI2C_Byte(0x0f); -+// -+// printk("\r\n0x0c~0e = %02x, %02x, %02x",reg_920c, reg_920d, reg_920e); -+// printk("\r\nEnter the dds_clock_debug cycle"); -+// -+// msleep(1000); -+// } -+// #endif -+//} -+ -+void pattern_test(void) -+{ -+ u32 DDS_initial_value; -+ u8 pclk_Mhz; -+ -+// video = &video_640x480_60Hz; -+// video = &video_720x480_60Hz; -+// video = &video_800x600_60Hz; -+// video = &video_1280x720_60Hz; -+// video = &video_1280x800_60Hz; -+ video = &video_1920x1080_60Hz; -+ -+ DigitalClockEn(); -+ TxAnalog(); -+ CbusAnalog(); -+ HDMIPllAnalog(); -+ AudioIIsEn(); -+ AviInfoframe(video); -+ lvds_output_cfg(); -+ -+ I2CADR = 0x92; -+ //////////////////Pattern resolution set//////////////////// -+ HDMI_WriteI2C_Byte(0x72,0x12); -+ HDMI_WriteI2C_Byte(0x73,(u8)((video->hs+video->hbp)%256)); //RGD_PTN_DE_DLY[7:0] -+ HDMI_WriteI2C_Byte(0x74,(u8)((video->hs+video->hbp)/256)); //RGD_PTN_DE_DLY[11:8] -+ HDMI_WriteI2C_Byte(0x75,(u8)((video->vs+video->vbp)%256)); //RGD_PTN_DE_TOP[6:0] -+ HDMI_WriteI2C_Byte(0x76,(u8)(video->hact%256)); //RGD_PTN_DE_CNT[7:0] -+ HDMI_WriteI2C_Byte(0x77,(u8)(video->vact%256)); //RGD_PTN_DE_LIN[7:0] -+ HDMI_WriteI2C_Byte(0x78,((((u8)(video->vact/256))<<4)+((u8)(video->hact/256)))); //RGD_PTN_DE_LIN[10:8],RGD_PTN_DE_CNT[11:8] -+ HDMI_WriteI2C_Byte(0x79,(u8)(video->htotal%256)); //RGD_PTN_H_TOTAL[7:0] -+ HDMI_WriteI2C_Byte(0x7a,(u8)(video->vtotal%256)); //RGD_PTN_V_TOTAL[7:0] -+ HDMI_WriteI2C_Byte(0x7b,((((u8)(video->vtotal/256))<<4)+((u8)(video->htotal/256)))); //RGD_PTN_V_TOTAL[10:8],RGD_PTN_H_TOTAL[11:8] -+ HDMI_WriteI2C_Byte(0x7c,(u8)(video->hs%256)); //RGD_PTN_HWIDTH[7:0] -+ HDMI_WriteI2C_Byte(0x7d,((((u8)(video->hs/256))<<6)+((u8)(video->vs%256)))); //RGD_PTN_HWIDTH[9:8],RGD_PTN_VWIDTH[5:0] -+ HDMI_WriteI2C_Byte(0x70,0x80); //pattern enable -+ HDMI_WriteI2C_Byte(0x71,0x51); -+ HDMI_WriteI2C_Byte(0x42,0x12); -+ /////////////////////////////////////////////////////////// -+ -+ HDMI_WriteI2C_Byte(0x1e,0x67); //h v d pol hdmi sel pll sel -+ -+ //////////////////pattern pixl clock set/////////////////// -+ pclk_Mhz = (u8)(video->pclk_khz/1000); -+ DDS_initial_value = (u32)(pclk_Mhz*0x16C16); -+ HDMI_WriteI2C_Byte(0x4e,(u8)(DDS_initial_value&0x000000ff)); //strm_sw_freq_word[ 7: 0] -+ HDMI_WriteI2C_Byte(0x4f,(u8)((DDS_initial_value&0x0000ff00)>>8)); //strm_sw_freq_word[15: 8] -+ HDMI_WriteI2C_Byte(0x50,(u8)((DDS_initial_value&0x00ff0000)>>16)); //strm_sw_freq_word[23:16] -+ HDMI_WriteI2C_Byte(0x51,0x80); -+ -+// HDMI_WriteI2C_Byte(0x4e,0x3E); //strm_sw_freq_word[ 7: 0] -+// HDMI_WriteI2C_Byte(0x4f,0xE9); //strm_sw_freq_word[15: 8] -+// HDMI_WriteI2C_Byte(0x50,0xD3); //strm_sw_freq_word[23:16] -+// HDMI_WriteI2C_Byte(0x51,0x80); //pattern en -+ /////////////////////////////////////////////////////////// -+ -+ HdmiOutput(1); -+ LvdsOutput(1); -+} -+ -+ -+u8 LT8912_Get_HPD(void) -+{ -+ //(0x90)0xc1[bit7] description HPD is High or Low -+ I2CADR = 0x90; -+ if((HDMI_ReadI2C_Byte(0xc1)&0x80)==0x80) -+ { -+ printk("%s LT8912_Get_HPD: high\n",LOG_FLAG); -+ return 1; -+ } -+ else -+ { -+ printk("%s LT8912_Get_HPD: low\n",LOG_FLAG); -+ return 0; -+ } -+} -+ -+void LT8912B_chip_ID(void) -+{ -+ I2CADR=0x90; -+ printk("%s chip ID: 0x%x, 0x%x\n",LOG_FLAG,HDMI_ReadI2C_Byte(0x00), HDMI_ReadI2C_Byte(0x01)); -+} -+ -+ -+void LT8912B_Suspend(bool on) -+{ -+ //9mA,HPD detect is normal. -+ if(on) -+ { -+ if(!suspend_on) -+ { -+ // enter suspend mode -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte( 0x54, 0x1d ); -+ HDMI_WriteI2C_Byte( 0x51, 0x15 ); -+ HDMI_WriteI2C_Byte( 0x44, 0x31 ); -+ HDMI_WriteI2C_Byte( 0x41, 0xbd ); -+ HDMI_WriteI2C_Byte( 0x5c, 0x11 ); -+ suspend_on = 1; -+ printk("%s suspend on.\n",LOG_FLAG); -+ } -+ -+ }else{ -+ -+ if(suspend_on) -+ { -+ //exist suspend mode -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte( 0x5c, 0x10 ); -+ HDMI_WriteI2C_Byte( 0x54, 0x1c ); -+ HDMI_WriteI2C_Byte( 0x51, 0x2d ); -+ HDMI_WriteI2C_Byte( 0x44, 0x30 ); -+ HDMI_WriteI2C_Byte( 0x41, 0xbc ); -+ -+ msleep(10); -+ HDMI_WriteI2C_Byte(0x03,0x7f); -+ msleep(10); -+ HDMI_WriteI2C_Byte(0x03,0xff); -+ -+ HDMI_WriteI2C_Byte(0x05,0xfb); -+ msleep(10); -+ HDMI_WriteI2C_Byte(0x05,0xff); -+ suspend_on = 0; -+ printk("%s suspend off.\n",LOG_FLAG); -+ } -+ } -+} -+ -+ -+void LT8912B_Config(void) -+{ -+ LT8912B_chip_ID(); -+ -+ #ifdef _pattern_test_ -+ pattern_test(); -+ while(Main_Loop); -+ #else -+ DigitalClockEn(); -+ TxAnalog(); -+ CbusAnalog(); -+ HDMIPllAnalog(); -+ MipiAnalog(); -+ MipiBasicSet(); -+ DDSConfig(); -+ MIPI_Video_Setup(&video_1920x1080_60Hz); -+ MIPI_Input_det(); -+ AudioIIsEn(); -+ -+ -+ #ifdef dds_debug -+ lt8912_check_dds(); // can be removed when debug stage. -+ #endif -+ -+ #ifdef _lvds_bypass -+ lvds_output_cfg(); -+ LvdsOutput(1); -+ #endif -+ -+///////////////////////////////////////////////////////////// test use -+// HdmiOutput(1); -+// while(1); -+///////////////////////////////////////////////////////////// -+ -+ #ifdef _hdmi_output -+ if(LT8912_Get_HPD()) -+ { -+ if(!Tx_HPD) -+ { -+ HdmiOutput(1); -+ Tx_HPD = 1; -+ printk("%s LT8912_Get_HPD: high\n",LOG_FLAG); -+ } -+ -+ }else{ -+ -+ if(Tx_HPD) -+ { -+ LT8912B_Suspend(1); -+ printk("%s LT8912 Suspend!\n",LOG_FLAG); -+ HdmiOutput(0); -+ Tx_HPD = 0; -+ printk("%s LT8912_Get_HPD: low\n",LOG_FLAG); -+ } -+ } -+ #endif -+ -+ #endif -+ -+ while(Main_Loop) -+ { -+ MIPI_Input_det(); -+ msleep(300); -+ -+ #ifdef _hdmi_output -+ if(LT8912_Get_HPD()) -+ { -+ if(!Tx_HPD) -+ { -+ LT8912B_Suspend(0); -+ HdmiOutput(1); -+ Tx_HPD = 1; -+ } -+ -+ }else{ -+ -+ if(Tx_HPD) -+ { -+ LT8912B_Suspend(1); -+ HdmiOutput(0); -+ Tx_HPD = 0; -+ } -+ } -+ #endif -+ } -+} -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B_Main.c b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B_Main.c -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B_Main.c -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B_Main.c -@@ -0,0 +1,35 @@ -+#include "../include/include.h" -+ -+ -+void LT8912B_Power_On(void) -+{ -+ gpiod_set_value(lt8912b->power_gpio,1); -+ msleep(5); -+ printk("%s Set power High level.\n ",LOG_FLAG); -+ -+} -+ -+void LT8912B_Reset(void) -+{ -+ //complete chip reset logic -+ gpiod_set_value(lt8912b->reset_gpio,1); -+ msleep(5); -+ gpiod_set_value(lt8912b->reset_gpio,0); -+ msleep(5); -+ gpiod_set_value(lt8912b->reset_gpio,1); -+ msleep(100); -+ printk("%s Reset chip.\n",LOG_FLAG); -+} -+ -+ -+int LT8912B_Main(void *data) -+{ -+ printk("%s Init Start!\n",LOG_FLAG); -+ LT8912B_Power_On(); -+ LT8912B_Reset(); -+ LT8912B_Config(); -+ -+ Tx_HPD = 0; -+ -+ return 0; -+} -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LontiumDrv.c b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LontiumDrv.c -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LontiumDrv.c -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LontiumDrv.c -@@ -0,0 +1,386 @@ -+#include "../include/include.h" -+ -+ -+struct _lt8912b *lt8912b; -+static struct task_struct *kthread_obj; -+volatile bool Main_Loop=true; -+char *ChipName = "lt8912b"; //Define Lontium Chip Name -+static int major = 0; -+static struct cdev chip_cdev; -+static struct class *chip_class; -+const char *LOG_FLAG = "LT8912B"; -+ -+u8 I2CADR; -+u8 addr_1_value = 0x00; -+u8 addr_2_value = 0x00; -+ -+ -+static int chip_open(struct inode *inode, struct file *filp) -+{ -+ printk("chip open\n"); -+ return 0; -+} -+ -+ -+static int chip_close (struct inode *node, struct file *file) -+{ -+ printk("chip close\n"); -+ return 0; -+} -+ -+ -+static ssize_t chip_read(struct file *filp, char __user *buf, size_t cnt, loff_t *offt) -+{ -+ Chip_Control_Args parameter; -+ -+ if (copy_from_user(¶meter, buf, sizeof(parameter))) { -+ return -EFAULT; -+ } -+ -+ parameter.value = HDMI_ReadI2C_Byte(parameter.address); -+ -+ if (copy_to_user(buf, ¶meter, sizeof(parameter))) { -+ return -EFAULT; -+ } -+ -+ return sizeof(parameter); -+ -+} -+ -+static ssize_t chip_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt) -+{ -+ Chip_Control_Args parameter; -+ -+ if (copy_from_user(¶meter, buf, sizeof(parameter))) { -+ return -EFAULT; -+ } -+ -+ HDMI_WriteI2C_Byte(parameter.address, parameter.value); -+ -+ return sizeof(parameter); -+ -+} -+ -+ -+ -+ -+static struct file_operations chip_drv = { -+ .owner = THIS_MODULE, -+ .open = chip_open, -+ .release = chip_close, -+ .read = chip_read, -+ .write = chip_write, -+}; -+ -+ -+ -+static int chip_dev_init(void) -+{ -+ int ret; -+ dev_t devid; -+ -+ ret = alloc_chrdev_region(&devid, 0, 1, ChipName); -+ if (ret < 0) { -+ return ret; -+ } -+ -+ major = MAJOR(devid); -+ cdev_init(&chip_cdev, &chip_drv); -+ cdev_add(&chip_cdev, devid, 1); -+ chip_class = class_create(THIS_MODULE, "chip_class"); -+ if (IS_ERR(chip_class)) { -+ unregister_chrdev(major, ChipName); -+ return -1; -+ } -+ -+ device_create(chip_class, NULL, MKDEV(major, 0), NULL, ChipName); /* /dev/ChipName */ -+ -+ return 0; -+} -+ -+ -+static void chip_dev_exit(void) -+{ -+ device_destroy(chip_class, MKDEV(major, 0)); -+ class_destroy(chip_class); -+ cdev_del(&chip_cdev); -+ unregister_chrdev_region(MKDEV(major,0), 1); -+} -+ -+ -+ -+static const struct regmap_range chip_ranges[] = { -+ { .range_min = 0, .range_max = 0xffff }, -+}; -+ -+static const struct regmap_access_table chip_table = { -+ .yes_ranges = chip_ranges, -+ .n_yes_ranges = ARRAY_SIZE(chip_ranges), -+}; -+ -+static const struct regmap_config chip_regmap_config = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .volatile_table = &chip_table, -+ .cache_type = REGCACHE_NONE, -+}; -+ -+ -+ -+static int chip_parse_dts(struct device *dev) -+{ -+ -+ /* -+ * devm_gpiod_get_optional - If this fails, NULL is returned and no error pointer. -+ * -+ * devm_gpiod_get - If this fails, an error pointer is returned, usually ERR_PTR(-ENOENT). -+ * -+ * The devm_gpiod_get function is recommended for practical use. -+ */ -+ -+ -+ //Gets the handle to power gpio in dts -+ -+#if 1 -+ lt8912b->power_gpio=devm_gpiod_get_optional(dev, "power", GPIOD_OUT_HIGH); -+ if (IS_ERR(lt8912b->power_gpio)) { -+ dev_err(dev, "Failed to get power GPIO\n"); -+ return PTR_ERR(lt8912b->power_gpio); -+ } -+#endif -+ -+ //Gets the handle to reset gpio in dts -+ -+ lt8912b->reset_gpio=devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); -+ if (IS_ERR(lt8912b->reset_gpio)) { -+ dev_err(dev, "Failed to get reset GPIO\n"); -+ return PTR_ERR(lt8912b->reset_gpio); -+ } -+ -+ -+ // Additional GPIO pins can be added here if needed -+ -+ return 0; -+} -+ -+ -+static int chip_probe(struct i2c_client *client, const struct i2c_device_id *id) -+{ -+ struct i2c_board_info addr_1_board_info = { -+ I2C_BOARD_INFO("lt8912b_addr_1", addr_1_value), -+ }; -+ struct i2c_board_info addr_2_board_info = { -+ I2C_BOARD_INFO("lt8912b_addr_2", addr_2_value), -+ }; -+ struct device_node *np = client->dev.of_node; -+ struct device_node *addr_1_node; -+ struct device_node *addr_2_node; -+ int ret; -+ -+ if (!np) { -+ dev_err(&client->dev, "Device tree node missing"); -+ return -EINVAL; -+ } -+ -+ chip_dev_init(); -+ -+ lt8912b = devm_kzalloc(&client->dev, sizeof(*lt8912b), GFP_KERNEL); -+ if (lt8912b == NULL) -+ return -ENOMEM; -+ -+ lt8912b->i2c_stu = client; -+ -+ lt8912b->dev = &client->dev; -+ -+ //////////////////////////////////////////////// -+ //addr_0 -+ -+ lt8912b->chip_regmap = devm_regmap_init_i2c(client, &chip_regmap_config); -+ if (IS_ERR(lt8912b->chip_regmap)) { -+ dev_err(&client->dev, "Failed to initialize regmap\n"); -+ return PTR_ERR(lt8912b->chip_regmap); -+ } -+ -+ //////////////////////////////////////////////// -+ -+ ///////////////////////////////////////////////// -+ //addr_1 -+ -+ addr_1_node = of_get_child_by_name(np, "lt8912b_addr_1"); -+ if (!addr_1_node) { -+ dev_err(&client->dev, "Failed to find lt8912b_addr_1 node"); -+ return -EINVAL; -+ } -+ -+ lt8912b->addr_1 = devm_kzalloc(&client->dev, sizeof(struct addr_1), GFP_KERNEL); -+ if (!lt8912b->addr_1) -+ return -ENOMEM; -+ -+ if (of_property_read_u8(addr_1_node, "addr_1_reg", &addr_1_value)) { -+ dev_err(&client->dev, "Failed to get addr_1_reg address"); -+ return -EINVAL; -+ } -+ addr_1_board_info.addr =addr_1_value; -+ -+ lt8912b->addr_1->i2c_stu = i2c_new_device(client->adapter, &addr_1_board_info); -+ if (!lt8912b->addr_1->i2c_stu) { -+ dev_err(&client->dev, "Failed to create I2C client for addr_1"); -+ return -ENODEV; -+ } -+ -+ lt8912b->addr_1->regmap = devm_regmap_init_i2c(lt8912b->addr_1->i2c_stu, &chip_regmap_config); -+ if (IS_ERR(lt8912b->addr_1->regmap)) { -+ dev_err(&client->dev, "Failed to initialize addr_1 regmap"); -+ i2c_unregister_device(lt8912b->addr_1->i2c_stu); -+ return PTR_ERR(lt8912b->addr_1->regmap); -+ } -+ -+ /////////////////////////////////////////////////// -+ -+ ///////////////////////////////////////////////// -+ //addr_2 -+ -+ addr_2_node = of_get_child_by_name(np, "lt8912b_addr_2"); -+ if (!addr_2_node) { -+ dev_err(&client->dev, "Failed to find lt8912b_addr_2 node"); -+ return -EINVAL; -+ } -+ -+ lt8912b->addr_2 = devm_kzalloc(&client->dev, sizeof(struct addr_2), GFP_KERNEL); -+ if (!lt8912b->addr_2) -+ return -ENOMEM; -+ -+ if (of_property_read_u8(addr_2_node, "addr_2_reg", &addr_2_value)) { -+ dev_err(&client->dev, "Failed to get addr_2_reg address"); -+ return -EINVAL; -+ } -+ addr_2_board_info.addr =addr_2_value; -+ -+ lt8912b->addr_2->i2c_stu = i2c_new_device(client->adapter, &addr_2_board_info); -+ if (!lt8912b->addr_2->i2c_stu) { -+ dev_err(&client->dev, "Failed to create I2C client for addr_2"); -+ return -ENODEV; -+ } -+ -+ lt8912b->addr_2->regmap = devm_regmap_init_i2c(lt8912b->addr_2->i2c_stu, &chip_regmap_config); -+ if (IS_ERR(lt8912b->addr_2->regmap)) { -+ dev_err(&client->dev, "Failed to initialize addr_2 regmap"); -+ i2c_unregister_device(lt8912b->addr_2->i2c_stu); -+ return PTR_ERR(lt8912b->addr_2->regmap); -+ } -+ /////////////////////////////////////////////////// -+ -+ mutex_init(<8912b->ocm_lock); -+ -+ ret = chip_parse_dts(lt8912b->dev); -+ if (ret<0){ -+ dev_err(&client->dev, "Failed to parse device tree\n"); -+ return ret; -+ } -+ -+ i2c_set_clientdata(client, lt8912b); -+ -+ -+ kthread_obj = kthread_run(LT8912B_Main, NULL, "LT8912B_kthread"); -+ if (IS_ERR(kthread_obj)) { -+ dev_err(&client->dev, "Failed to create kernel thread\n"); -+ return PTR_ERR(kthread_obj); -+ } -+ -+ return 0; -+ -+} -+ -+static int chip_remove(struct i2c_client *client) -+{ -+ -+ Main_Loop = false; -+ msleep(500); -+ -+ mutex_destroy(<8912b->ocm_lock); -+ -+ i2c_unregister_device(lt8912b->addr_1->i2c_stu); -+ -+ i2c_unregister_device(lt8912b->addr_2->i2c_stu); -+ -+ chip_dev_exit(); -+ -+ printk("driver removed\n"); -+ return 0; -+} -+ -+ -+static int chip_suspend(struct device *dev) -+{ -+ -+ printk(KERN_INFO "%s Suspend.\n",LOG_FLAG); -+ -+ gpiod_set_value(lt8912b->reset_gpio,0); -+ msleep(10); -+ -+ Main_Loop =false; -+ -+ return 0; -+} -+ -+ -+ -+static int chip_resume(struct device *dev) -+{ -+ -+ printk(KERN_INFO "%s Resume.\n",LOG_FLAG); -+ -+ -+ gpiod_set_value(lt8912b->reset_gpio,1); -+ msleep(5); -+ -+ Main_Loop = true; -+ msleep(5); -+ -+ kthread_obj = kthread_run(LT8912B_Main, NULL, "LT8912B_kthread"); -+ -+ return 0; -+} -+ -+ -+static const struct dev_pm_ops chip_pm_ops = { -+ .suspend = chip_suspend, -+ .resume = chip_resume, -+}; -+ -+ -+ -+ -+static const struct i2c_device_id chip_ids[] = { -+ {"lt8912b", 0}, -+ { } -+}; -+MODULE_DEVICE_TABLE(i2c, chip_ids); -+ -+ -+static const struct of_device_id chip_id_table[] = { -+ {.compatible = "lontium,lt8912b"}, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, chip_id_table); -+ -+ -+static struct i2c_driver chip_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "lt8912b", -+ .pm = &chip_pm_ops, -+ .of_match_table = chip_id_table, -+ -+ }, -+ .probe = chip_probe, -+ .remove = chip_remove, -+ .id_table = chip_ids, -+}; -+ -+ -+module_i2c_driver(chip_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("LT8912B driver"); -+MODULE_AUTHOR("Tony Yang"); -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/src/OcmI2cMaster.c b/source/kernel/kernel5.4/drivers/video/LT8912B/src/OcmI2cMaster.c -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/src/OcmI2cMaster.c -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/src/OcmI2cMaster.c -@@ -0,0 +1,91 @@ -+#include "../include/include.h" -+ -+ -+ -+ -+ -+int HDMI_WriteI2C_Byte(u8 addr,u8 data) -+{ -+ int ret = 0; -+ mutex_lock(<8912b->ocm_lock); -+ -+ if(I2CADR==0x90) -+ { -+ ret = regmap_write(lt8912b->chip_regmap, addr, data); -+ if (ret < 0) { -+ printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d", -+ lt8912b->i2c_stu->addr, addr, data, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ }else if(I2CADR==0x92){ -+ ret = regmap_write(lt8912b->addr_1->regmap, addr, data); -+ if (ret < 0) { -+ printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d", -+ lt8912b->addr_1->i2c_stu->addr, addr, data, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ -+ }else if(I2CADR==0x94){ -+ ret = regmap_write(lt8912b->addr_2->regmap, addr, data); -+ if (ret < 0) { -+ printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d", -+ lt8912b->addr_2->i2c_stu->addr, addr, data, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ } -+ -+ mutex_unlock(<8912b->ocm_lock); -+ return 0; -+} -+ -+ -+ -+ -+ -+int HDMI_ReadI2C_Byte(u8 addr) -+{ -+ int ret = 0; -+ unsigned int val = 0; -+ mutex_lock(<8912b->ocm_lock); -+ -+ if(I2CADR==0x90){ -+ -+ ret = regmap_read(lt8912b->chip_regmap, addr, &val); -+ if (ret < 0) { -+ printk("regmap_read error: (0x%02x 0x%02x) %d", -+ lt8912b->i2c_stu->addr, addr, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ }else if(I2CADR==0x92){ -+ -+ ret = regmap_read(lt8912b->addr_1->regmap, addr, &val); -+ if (ret < 0) { -+ printk("regmap_read error: (0x%02x 0x%02x) %d", -+ lt8912b->addr_1->i2c_stu->addr, addr, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ -+ }else if(I2CADR==0x94){ -+ -+ ret = regmap_read(lt8912b->addr_2->regmap, addr, &val); -+ if (ret < 0) { -+ printk("regmap_read error: (0x%02x 0x%02x) %d", -+ lt8912b->addr_2->i2c_stu->addr, addr, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ -+ } -+ -+ mutex_unlock(<8912b->ocm_lock); -+ return (u8)val; -+} -+ -+ -+EXPORT_SYMBOL(HDMI_WriteI2C_Byte); -+EXPORT_SYMBOL(HDMI_ReadI2C_Byte); -diff --git a/source/bsp/u-boot22/arch/arm/dts/uis7885_2h10.dts b/source/bsp/u-boot22/arch/arm/dts/uis7885_2h10.dts -index 38a049e987..311964869c 100644 ---- a/source/bsp/u-boot22/arch/arm/dts/uis7885_2h10.dts -+++ b/source/bsp/u-boot22/arch/arm/dts/uis7885_2h10.dts -@@ -9,7 +9,7 @@ - #include "lcd/lcd_g40396_truly_mipi_fhd.dtsi" - #include "lcd/lcd_nt36672e_truly_mipi_fhd_nodsc.dtsi" - #include "lcd/lcd_ili7806s_truly_mipi_hdplus.dtsi" --#include "lcd/lcd_dummy_mipi.dtsi" -+#include "lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi" - #include - #include - -@@ -72,7 +72,7 @@ - reg = <0x0 0x92200000 0x0 0x00200000>; - }; - -- pre_log_buffer: pre_log_buffer@92300000{ -+ pre_log_buffer: pre_log_buffer@b4000000{ - reg = <0x0 0xb4000000 0x0 0x00002000>; - }; - -@@ -89,8 +89,8 @@ - reg = <0x0 0xbd060000 0x0 0x01fa0000>; - }; - -- tos_shm_reserved: sh-mem@96000000{ -- reg = <0x0 0x96000000 0x0 0x00100000>; -+ tos_shm_reserved: sh-mem@C3000000{ -+ reg = <0x0 0xC3000000 0x0 0x00100000>; - }; - - secboot_arg_reserved: secboot-arg-mem@98100000{ -diff --git a/source/bsp/u-boot22/board/sprd/uis7885_2h10/pinmap-ums9620.c b/source/bsp/u-boot22/board/sprd/uis7885_2h10/pinmap-ums9620.c -index 28addeca94..933d4f4024 100644 ---- a/source/bsp/u-boot22/board/sprd/uis7885_2h10/pinmap-ums9620.c -+++ b/source/bsp/u-boot22/board/sprd/uis7885_2h10/pinmap-ums9620.c -@@ -35,13 +35,13 @@ static struct pinmap_t pinmap[] = { - //{REG_PIN_PWR_PAD_CTL_RESERVED,0x00000000},// - {REG_PIN_SIM_MATRIX_MTX_CFG, 0x00000002},//SIM0->PSCP_SIM0;SIM1->PSCP_SIM1; - {REG_PIN_DMIC_MATRIX_MTX_CFG, 0x00000000},//DMIC0->AUDCP_AUD_DMIC0;DMIC1->AUDCP_AUD_DMIC1;DMIC2->AUDCP_PDM_DMIC2 --{REG_PIN_UART_MATRIX_MTX_CFG, 0x5B97081A},//UART0->CM4_UART1;UART1->AP_UART1;UART2->AP_UART2;UART3->PHYCP_WCI2;UART4->CM4_UART0;UART5->CM4_UART2;UART6->PSCP_UART1; --{REG_PIN_UART_MATRIX_MTX_CFG1, 0x00000086},//UART7->PHYCP_UART0;UART8->AUDDSP_UART0; -+{REG_PIN_UART_MATRIX_MTX_CFG, 0x3B97081A},//UART0->CM4_UART1;UART1->AP_UART1;UART2->AP_UART2;UART3->PHYCP_WCI2;UART4->CM4_UART0;UART5->CM4_UART2;UART6->AP_UART3; -+{REG_PIN_UART_MATRIX_MTX_CFG1, 0x00000080},//UART7->AP_UART0;UART8->AUDDSP_UART0; - {REG_PIN_IIS_MATRIX_MTX_CFG, 0x02904080},//IIS0->AP_IIS0;IIS1->AP_IIS1;IIS2->AP_IIS2;IIS3->AUDCP_IIS0;IIS4->AUDCP_IIS1; - {REG_PIN_IIS_MATRIX_MTX_CFG1, 0x00000006},//IIS5->AUDCP_IIS2;IIS6->vbc_IIS2; - {REG_PIN_SPI_MATRIX_MTX_CFG, 0x00000040},//SPI0->AP_SPI0;SPI1->AP_SPI1;SPI2->AP_SPI2;SPI3->CM4_SPI0; --{REG_PIN_IIC_MATRIX_MTX_CFG, 0x76D23C10},//IIC0->AP_IIC0;IIC1->AP_IIC1;IIC2->CM4_I2C0;IIC3->AP_IIC3;IIC4->AP_IIC2;IIC5->CM4_I2C1;IIC6->AP_IIC6;IIC7->AP_IIC7 --{REG_PIN_IIC_MATRIX_MTX_CFG1, 0x0000054},//IIC8->AP_IIC4;IIC9->AP_IIC5 -+{REG_PIN_IIC_MATRIX_MTX_CFG, 0x76523C10},//IIC0->AP_IIC0;IIC1->AP_IIC1;IIC2->CM4_I2C0;IIC3->AP_IIC3;IIC4->AP_IIC2;IIC5->AP_I2C5;IIC6->AP_IIC6;IIC7->AP_IIC7 -+{REG_PIN_IIC_MATRIX_MTX_CFG1, 0x000000D4},//IIC8->AP_IIC4;IIC9->CM4_IIC1 - {REG_PIN_HOT_PLUG_DET_MATRIX_MTX_CFG, 0x00000000},//HOTPLUG0->SIM0;HOTPLUG1->SIM1;HOTPLUG2->AP_SDIO0 - - //REG_PIN_xx Function select -@@ -86,10 +86,10 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_EXTINT0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//CTP_INT - {REG_PIN_EXTINT1, BITS_PIN_AF(3)}, - {REG_MISC_PIN_EXTINT1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CTP_RST --{REG_PIN_SDA3, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SDA3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_SCL3, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SCL3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_PIN_SDA3, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SDA3, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//HDMI conn I2C -+{REG_PIN_SCL3, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SCL3, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//HDMI conn I2C - {REG_PIN_DCDC_ARM1_EN, BITS_PIN_AF(0)}, - {REG_MISC_PIN_DCDC_ARM1_EN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//VDDCPU1_EN - {REG_PIN_PTEST, BITS_PIN_AF(0)}, -@@ -144,20 +144,20 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_TF_DET, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//TF_DET - {REG_PIN_BAT_DET, BITS_PIN_AF(0)}, - {REG_MISC_PIN_BAT_DET, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//BAT_DET --{REG_PIN_SCL4, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SCL4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_SDA4, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SDA4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_PIN_SCL4, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SCL4, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//HDMI/CTP I2C -+{REG_PIN_SDA4, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SDA4, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//HDMI/CTP I2C - {REG_PIN_CLK_AUX1, BITS_PIN_AF(0)}, - {REG_MISC_PIN_CLK_AUX1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CLK_AUX1 --{REG_PIN_IIS1DI, BITS_PIN_AF(2)}, --{REG_MISC_PIN_IIS1DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//FTID_INT --{REG_PIN_IIS1DO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS1DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//FTID_RSTN --{REG_PIN_IIS1CLK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS1CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAMERA_FLASH_EN --{REG_PIN_IIS1LRCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS1LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//camera_torch_en -+{REG_PIN_IIS1DI, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS1DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//40PIN PCM_DI -+{REG_PIN_IIS1DO, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS1DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//40PIN PCM_DO -+{REG_PIN_IIS1CLK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS1CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_OE},//40PIN PCM_CLK -+{REG_PIN_IIS1LRCK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS1LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//40PIN PCM_SYNC - {REG_PIN_SIMCLK0, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SIMCLK0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_NONE | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//SIM0_CLK - {REG_PIN_SIMDA0, BITS_PIN_AF(0)}, -@@ -171,39 +171,39 @@ static struct pinmap_t pinmap[] = { - {REG_PIN_SIMRST1, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SIMRST1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_NONE | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//SIM1_RST - {REG_PIN_SD0_CMD, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_CMD, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_CMD -+{REG_MISC_PIN_SD0_CMD, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_CMD - {REG_PIN_SD0_D_0, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_D_0, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D0 -+{REG_MISC_PIN_SD0_D_0, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D0 - {REG_PIN_SD0_D_1, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_D_1, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D1 -+{REG_MISC_PIN_SD0_D_1, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D1 - {REG_PIN_SD0_CLK, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_CLK, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_CLK0 -+{REG_MISC_PIN_SD0_CLK, BITS_PIN_DS(6) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_CLK0 - {REG_PIN_SD0_D_2, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_D_2, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D2 -+{REG_MISC_PIN_SD0_D_2, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D2 - {REG_PIN_SD0_D_3, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_D_3, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D3 --{REG_PIN_SD2_CMD, BITS_PIN_AF(1)}, --{REG_MISC_PIN_SD2_CMD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//LCM_SPI_MISO --{REG_PIN_SD2_D0, BITS_PIN_AF(1)}, --{REG_MISC_PIN_SD2_D0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//LCM_SPI_MOSI --{REG_PIN_SD2_D1, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SD2_D1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAMERA_FLASH_CHIPEN --{REG_PIN_SD2_CLK, BITS_PIN_AF(1)}, --{REG_MISC_PIN_SD2_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//LCM_SPI_CLK --{REG_PIN_SD2_D2, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SD2_D2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//UCP1301_RSTN --{REG_PIN_SD2_D3, BITS_PIN_AF(1)}, --{REG_MISC_PIN_SD2_D3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_SPI_CS -+{REG_MISC_PIN_SD0_D_3, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D3 -+{REG_PIN_SD2_CMD, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_CMD, BITS_PIN_DS(4) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD2_CMD -+{REG_PIN_SD2_D0, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_D0, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF__SD2_D0 -+{REG_PIN_SD2_D1, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_D1, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD2_D1 -+{REG_PIN_SD2_CLK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_CLK, BITS_PIN_DS(4) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD2_CLK -+{REG_PIN_SD2_D2, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_D2, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD2_D2 -+{REG_PIN_SD2_D3, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_D3, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD2_D3 - {REG_PIN_IIS3DI, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS3DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_SOURCE_AVEEEN -+{REG_MISC_PIN_IIS3DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC - {REG_PIN_IIS3DO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS3DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_SOURCE_AVDDEN --{REG_PIN_IIS3LRCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS3LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//BQ25970_INTacticelow --{REG_PIN_IIS3CLK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS3CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//TOF_XSHUT -+{REG_MISC_PIN_IIS3DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//SPI1_CS1 ? -+{REG_PIN_IIS3LRCK, BITS_PIN_AF(1)}, -+{REG_MISC_PIN_IIS3LRCK, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C7 -+{REG_PIN_IIS3CLK, BITS_PIN_AF(1)}, -+{REG_MISC_PIN_IIS3CLK, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C7 - {REG_PIN_CLK_AUX2, BITS_PIN_AF(0)}, --{REG_MISC_PIN_CLK_AUX2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CLK_AUX2 -+{REG_MISC_PIN_CLK_AUX2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//clk AUX2 test point - {REG_PIN_RFCTL_0, BITS_PIN_AF(0)}, - {REG_MISC_PIN_RFCTL_0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_0 - {REG_PIN_RFCTL_1, BITS_PIN_AF(0)}, -@@ -222,20 +222,20 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_RFCTL_7, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_7 - {REG_PIN_RFCTL_8, BITS_PIN_AF(0)}, - {REG_MISC_PIN_RFCTL_8, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_8 --{REG_PIN_RFCTL_9, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFCTL_9, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//VDDCAMMOT_EN --{REG_PIN_RFCTL_10, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFCTL_10, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//VDDCAMA1_EN -+{REG_PIN_RFCTL_9, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFCTL_9, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_9 -+{REG_PIN_RFCTL_10, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFCTL_10, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_10 - {REG_PIN_RFCTL_11, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFCTL_11, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//VDDCAMA0_EN --{REG_PIN_RFCTL_12, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFCTL_12, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//VDDCAMCORE_EN -+{REG_MISC_PIN_RFCTL_11, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_PIN_RFCTL_12, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFCTL_12, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_12 - {REG_PIN_RFCTL_13, BITS_PIN_AF(0)}, - {REG_MISC_PIN_RFCTL_13, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//GNSS_COEXIST - {REG_PIN_RFCTL_14, BITS_PIN_AF(1)}, - {REG_MISC_PIN_RFCTL_14, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//WB_WCI_2_RXD - {REG_PIN_RFCTL_15, BITS_PIN_AF(1)}, --{REG_MISC_PIN_RFCTL_15, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//WB_WCI_2_RXD -+{REG_MISC_PIN_RFCTL_15, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//WB_WCI_2_TXD - {REG_PIN_RFFE0_SCK, BITS_PIN_AF(0)}, - {REG_MISC_PIN_RFFE0_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SCK0 - {REG_PIN_RFFE0_SDA, BITS_PIN_AF(0)}, -@@ -256,16 +256,16 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_RFFE4_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SCK4 - {REG_PIN_RFFE4_SDA, BITS_PIN_AF(0)}, - {REG_MISC_PIN_RFFE4_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SDA4 --{REG_PIN_RFFE5_SCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFFE5_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_RFFE5_SDA, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFFE5_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_RFFE6_SCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFFE6_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_RFFE6_SDA, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFFE6_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_PIN_RFFE5_SCK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFFE5_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SCK5 -+{REG_PIN_RFFE5_SDA, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFFE5_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SDA5 -+{REG_PIN_RFFE6_SCK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFFE6_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SCK6 -+{REG_PIN_RFFE6_SDA, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFFE6_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SDA6 - {REG_PIN_RFFE7_SCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFFE7_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_RFFE7_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//HDMI_PWR_5V - {REG_PIN_RFFE7_SDA, BITS_PIN_AF(3)}, - {REG_MISC_PIN_RFFE7_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC - {REG_PIN_LVDSRF_ADDAC0_ON, BITS_PIN_AF(0)}, -@@ -293,31 +293,31 @@ static struct pinmap_t pinmap[] = { - {REG_PIN_SDA6, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SDA6, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C6_SDA - {REG_PIN_VDSP_TDO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_VDSP_TDO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_VDSP_TDO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//LCM_INT1 - {REG_PIN_VDSP_TDI, BITS_PIN_AF(3)}, --{REG_MISC_PIN_VDSP_TDI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_VDSP_TDI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//LCM_INT/LT8912B - {REG_PIN_VDSP_TMS, BITS_PIN_AF(3)}, - {REG_MISC_PIN_VDSP_TMS, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_Z},//BOARD_ID0 - {REG_PIN_VDSP_TCK, BITS_PIN_AF(3)}, - {REG_MISC_PIN_VDSP_TCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_Z},//BOARD_ID1 - {REG_PIN_VDSP_RTCK, BITS_PIN_AF(3)}, - {REG_MISC_PIN_VDSP_RTCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_Z},//BOARD_ID2 --{REG_PIN_DMIC_CLK2, BITS_PIN_AF(0)}, --{REG_MISC_PIN_DMIC_CLK2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//PDM_CLK2 --{REG_PIN_DMIC_DATA2, BITS_PIN_AF(0)}, --{REG_MISC_PIN_DMIC_DATA2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//PDM_DATA2 -+{REG_PIN_DMIC_CLK2, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_DMIC_CLK2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_PIN_DMIC_DATA2, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_DMIC_DATA2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC - {REG_PIN_DMIC_CLK0, BITS_PIN_AF(3)}, - {REG_MISC_PIN_DMIC_CLK0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//CHG_INT - {REG_PIN_DMIC_DATA0, BITS_PIN_AF(3)}, --{REG_MISC_PIN_DMIC_DATA0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_DMIC_DATA0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//HUB_LDO_EN - {REG_PIN_DMIC_CLK1, BITS_PIN_AF(3)}, --{REG_MISC_PIN_DMIC_CLK1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CHG_EN_N -+{REG_MISC_PIN_DMIC_CLK1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//HDMI_5V_EN - {REG_PIN_DMIC_DATA1, BITS_PIN_AF(3)}, --{REG_MISC_PIN_DMIC_DATA1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CHG_FLAG_N --{REG_PIN_U2TXD, BITS_PIN_AF(0)}, --{REG_MISC_PIN_U2TXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//BB_U2TXD --{REG_PIN_U2RXD, BITS_PIN_AF(0)}, --{REG_MISC_PIN_U2RXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//BB_U2RXD -+{REG_MISC_PIN_DMIC_DATA1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//USB_HOST_SW1 -+{REG_PIN_U2TXD, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_U2TXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//EXT_LEVLESHIFT_EN -+{REG_PIN_U2RXD, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_U2RXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//POE_PWR_OFF - {REG_PIN_U1TXD, BITS_PIN_AF(0)}, - {REG_MISC_PIN_U1TXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//BB_U1TXD - {REG_PIN_U1RXD, BITS_PIN_AF(0)}, -@@ -335,45 +335,45 @@ static struct pinmap_t pinmap[] = { - {REG_PIN_MTMS_ARM, BITS_PIN_AF(0)}, - {REG_MISC_PIN_MTMS_ARM, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_NONE | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//MTMS - {REG_PIN_AUD_DSP_TDO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_AUD_DSP_TDO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_AUD_DSP_TDO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//USBA_5V_EN - {REG_PIN_AUD_DSP_RTCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_AUD_DSP_RTCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_AUD_DSP_RTCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LAN_PWR_EN - {REG_PIN_AUD_DSP_TDI, BITS_PIN_AF(3)}, --{REG_MISC_PIN_AUD_DSP_TDI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_AUD_DSP_TDI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO148 - {REG_PIN_AUD_DSP_TCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_AUD_DSP_TCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//TOF_GPIO -+{REG_MISC_PIN_AUD_DSP_TCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC - {REG_PIN_AUD_DSP_TMS, BITS_PIN_AF(3)}, --{REG_MISC_PIN_AUD_DSP_TMS, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_AUD_DSP_TMS, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO150 - {REG_PIN_CMMCLK0, BITS_PIN_AF(0)}, --{REG_MISC_PIN_CMMCLK0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_MCLK0 -+{REG_MISC_PIN_CMMCLK0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMMCLK1, BITS_PIN_AF(0)}, - {REG_MISC_PIN_CMMCLK1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_MCLK1 - {REG_PIN_CMMCLK2, BITS_PIN_AF(0)}, - {REG_MISC_PIN_CMMCLK2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_MCLK2 - {REG_PIN_CMMCLK3, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMMCLK3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_CMMCLK3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMRST0, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMRST0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_RST0 -+{REG_MISC_PIN_CMRST0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMRST1, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMRST1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_RST1 -+{REG_MISC_PIN_CMRST1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMRST2, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMRST2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_RST2 -+{REG_MISC_PIN_CMRST2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//HUB_LDO_EN - {REG_PIN_CMRST3, BITS_PIN_AF(3)}, - {REG_MISC_PIN_CMRST3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_RST3 - {REG_PIN_CMRST4, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMRST4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_CMRST4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG5 - {REG_PIN_CMRST5, BITS_PIN_AF(3)}, - {REG_MISC_PIN_CMRST5, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_RST5 - {REG_PIN_CMPD0, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMPD0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_PWDN0 -+{REG_MISC_PIN_CMPD0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMPD1, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMPD1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_PWDN1 -+{REG_MISC_PIN_CMPD1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMPD2, BITS_PIN_AF(3)}, - {REG_MISC_PIN_CMPD2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_PWDN2 - {REG_PIN_CMPD3, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMPD3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_CMPD3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG4 - {REG_PIN_CMPD4, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMPD4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_CMPD4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG3 - {REG_PIN_CMPD5, BITS_PIN_AF(3)}, - {REG_MISC_PIN_CMPD5, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_PWDN5 - {REG_PIN_SCL0, BITS_PIN_AF(0)}, -@@ -389,17 +389,17 @@ static struct pinmap_t pinmap[] = { - {REG_PIN_SDA8, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SDA8, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C8_SDA - {REG_PIN_SCL9, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SCL9, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C9_SCL -+{REG_MISC_PIN_SCL9, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C9_SCL - {REG_PIN_SDA9, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SDA9, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C9_SDA -+{REG_MISC_PIN_SDA9, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C9_SDA - {REG_PIN_SPI3_CSN, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI3_CSN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//CAMERA_FLASH_SYNC -+{REG_MISC_PIN_SPI3_CSN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG3 - {REG_PIN_SPI3_CLK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI3_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//COLOR_SENSOR_INT -+{REG_MISC_PIN_SPI3_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG2 - {REG_PIN_SPI3_DI, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI3_DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//EAR_CTL1 -+{REG_MISC_PIN_SPI3_DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG1 - {REG_PIN_SPI3_DO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI3_DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//EAR_CTL2 -+{REG_MISC_PIN_SPI3_DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG0 - {REG_PIN_SPI0_CSN, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SPI0_CSN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//FTID_SPI_CS - {REG_PIN_SPI0_DO, BITS_PIN_AF(0)}, -@@ -412,46 +412,46 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_SCL2, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C2_SCL - {REG_PIN_SDA2, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SDA2, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C2_SDA --{REG_PIN_KEYOUT1, BITS_PIN_AF(2)}, --{REG_MISC_PIN_KEYOUT1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//PROX_INT --{REG_PIN_KEYOUT0, BITS_PIN_AF(2)}, --{REG_MISC_PIN_KEYOUT0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//AG_INT0 --{REG_PIN_KEYOUT2, BITS_PIN_AF(2)}, --{REG_MISC_PIN_KEYOUT2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//AG_INT1 -+{REG_PIN_KEYOUT1, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_KEYOUT1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINGT -+{REG_PIN_KEYOUT0, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_KEYOUT0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//USBA_CL_EN -+{REG_PIN_KEYOUT2, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_KEYOUT2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//EXT_XTL_EN4 - {REG_PIN_EXTINT9, BITS_PIN_AF(3)}, --{REG_MISC_PIN_EXTINT9, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//FS_EIS -+{REG_MISC_PIN_EXTINT9, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_Z},//LAN_PWR_EN - {REG_PIN_EXTINT10, BITS_PIN_AF(3)}, --{REG_MISC_PIN_EXTINT10, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//WCHG_INT -+{REG_MISC_PIN_EXTINT10, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//WB_TX_REQ - {REG_PIN_KEYIN0, BITS_PIN_AF(3)}, - {REG_MISC_PIN_KEYIN0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//KEYIN0 - {REG_PIN_KEYIN1, BITS_PIN_AF(3)}, - {REG_MISC_PIN_KEYIN1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//KETIN1 - {REG_PIN_KEYIN2, BITS_PIN_AF(3)}, --{REG_MISC_PIN_KEYIN2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//LCM_ID -+{REG_MISC_PIN_KEYIN2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_SPI2_CSN, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI2_CSN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_SPI2_CSN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//WB_INT - {REG_PIN_SPI2_DO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI2_DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_SPI2_DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_SOURCE_AVDDEN - {REG_PIN_SPI2_DI, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI2_DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_SPI2_DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//GPIO - {REG_PIN_SPI2_CLK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI2_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_SD1_CMD, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_CMD, BITS_PIN_DS(4) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_CMD --{REG_PIN_SD1_D0, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_D0, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_D0 --{REG_PIN_SD1_D1, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_D1, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_D1 --{REG_PIN_SD1_CLK, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_CLK, BITS_PIN_DS(4) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_CLK --{REG_PIN_SD1_D2, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_D2, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_D2 --{REG_PIN_SD1_D3, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_D3, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_D3 -+{REG_MISC_PIN_SPI2_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG4 -+{REG_PIN_SD1_CMD, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_SD1_CMD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL| BIT_PIN_SLP_OE},//WCN_CHIP_EN -+{REG_PIN_SD1_D0, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_SD1_D0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM1_RSTN -+{REG_PIN_SD1_D1, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_SD1_D1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM1_FMARK -+{REG_PIN_SD1_CLK, BITS_PIN_AF(1)}, -+{REG_MISC_PIN_SD1_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//PERST0_N -+{REG_PIN_SD1_D2, BITS_PIN_AF(1)}, -+{REG_MISC_PIN_SD1_D2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//PCIE3_CLKREQ -+{REG_PIN_SD1_D3, BITS_PIN_AF(1)}, -+{REG_MISC_PIN_SD1_D3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//PCIE3_WAKE - {REG_PIN_U5TXD, BITS_PIN_AF(1)}, --{REG_MISC_PIN_U5TXD, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C5_SCL -+{REG_MISC_PIN_U5TXD, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C5_SCL - {REG_PIN_U5RXD, BITS_PIN_AF(1)}, --{REG_MISC_PIN_U5RXD, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C5_SDA -+{REG_MISC_PIN_U5RXD, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C5_SDA - {REG_PIN_CLK_AUX0, BITS_PIN_AF(0)}, - {REG_MISC_PIN_CLK_AUX0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//WCN_32K_IN - {REG_PIN_U0TXD, BITS_PIN_AF(0)}, -@@ -470,18 +470,18 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_IIS0CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//BT_PCM_CLK - {REG_PIN_IIS0LRCK, BITS_PIN_AF(0)}, - {REG_MISC_PIN_IIS0LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//BT_PCM_SYNC --{REG_PIN_PWMC, BITS_PIN_AF(3)}, --{REG_MISC_PIN_PWMC, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//WF_HOST_WAKE --{REG_PIN_IIS4DO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS4DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//WB_CHIP_EN -+{REG_PIN_PWMC, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_PWMC, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//EXT_PWM -+{REG_PIN_IIS4DO, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS4DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_I2S_SDO /HDMI - {REG_PIN_IIS4DI, BITS_PIN_AF(3)}, - {REG_MISC_PIN_IIS4DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//WB_RST --{REG_PIN_IIS4CLK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS4CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//WB_INT --{REG_PIN_IIS4LRCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS4LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//WF_WAKE_HOST -+{REG_PIN_IIS4CLK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS4CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_I2S_CLK -+{REG_PIN_IIS4LRCK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS4LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_I2S_WS - {REG_PIN_ESE_GPIO_N, BITS_PIN_AF(0)}, --{REG_MISC_PIN_ESE_GPIO_N, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NFC_CLK_REQ -+{REG_MISC_PIN_ESE_GPIO_N, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC - {REG_PIN_U4TXD, BITS_PIN_AF(0)}, - {REG_MISC_PIN_U4TXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//GPS_U1RXD - {REG_PIN_U4RXD, BITS_PIN_AF(0)}, -diff --git a/source/bsp/u-boot22/drivers/video/sprd/dsi/mipi_dsi_api.c b/source/bsp/u-boot22/drivers/video/sprd/dsi/mipi_dsi_api.c -index cb361e6b9b..c27d96f707 100644 ---- a/source/bsp/u-boot22/drivers/video/sprd/dsi/mipi_dsi_api.c -+++ b/source/bsp/u-boot22/drivers/video/sprd/dsi/mipi_dsi_api.c -@@ -231,7 +231,8 @@ int mipi_dsi_dpi_video(struct sprd_dsi *dsi, struct dpi_video_param *param) - dsi_hal_vblk_cmd_trans_limit(dsi, 0x80); - if (!dsi->panel->hporch_lp_disable) - dsi_hal_dpi_hporch_lp_en(dsi, 1); -- dsi_hal_dpi_vporch_lp_en(dsi, 1); -+ dsi_hal_dpi_hporch_lp_en(dsi, 0); -+ dsi_hal_dpi_vporch_lp_en(dsi, 0); - dsi_hal_dpi_hsync_pol(dsi, param->hsync_pol); - dsi_hal_dpi_vsync_pol(dsi, param->vsync_pol); - dsi_hal_dpi_data_en_pol(dsi, param->de_pol); -diff --git a/source/bsp/u-boot22/drivers/video/sprd/sprd_panel.c b/source/bsp/u-boot22/drivers/video/sprd/sprd_panel.c -index a73c23999e..3383794042 100644 ---- a/source/bsp/u-boot22/drivers/video/sprd/sprd_panel.c -+++ b/source/bsp/u-boot22/drivers/video/sprd/sprd_panel.c -@@ -68,6 +68,11 @@ uint32_t load_lcd_id_to_kernel(void) - /* WORKAROUND: to keep the same order with sprdfb_panel.c */ - uint32_t load_lcd_width_to_kernel(void) - { -+ if (panel_drv && panel_drv->info && -+ panel_drv->info->lcd_name && -+ !strcmp(panel_drv->info->lcd_name, "lcd_dummy_mipi_hd")) -+ return panel_drv->info->width; -+ - if (panel_drv && panel_drv->info) - return panel_drv->info->height; - else -@@ -77,6 +82,11 @@ uint32_t load_lcd_width_to_kernel(void) - /* WORKAROUND: to keep the same order with sprdfb_panel.c */ - uint32_t load_lcd_hight_to_kernel(void) - { -+ if (panel_drv && panel_drv->info && -+ panel_drv->info->lcd_name && -+ !strcmp(panel_drv->info->lcd_name, "lcd_dummy_mipi_hd")) -+ return panel_drv->info->height; -+ - if (panel_drv && panel_drv->info) - return panel_drv->info->width; - else -diff --git a/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -new file mode 100644 ---- a/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -0,0 +1,57 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR MIT -+/* -+ * LT8912B MIPI-DSI to HDMI 1080p dummy panel config. -+ */ -+ -+/ { -+ lcds { -+ lcd_dummy_mipi_hd: lcd_dummy_mipi_hd { -+ sprd,dsi-work-mode = <2>; /* video pulse mode */ -+ sprd,dsi-lane-number = <4>; -+ sprd,dsi-color-format = "rgb888"; -+ -+ sprd,phy-bit-clock = <1200000>; /* kbps 921600 1200000 */ -+ sprd,phy-escape-clock = <20000>; /* kHz */ -+ sprd,video-lp-cmd-enable = <0>; -+ sprd,hporch-lp-disable = <1>; -+ sprd,width-mm = <121>; -+ sprd,height-mm = <68>; -+ sprd,esd-check-enable = <0>; -+ sprd,esd-check-mode = <1>; -+ sprd,esd-check-period = <1000>; -+ -+ /* panel interface type: 2:MIPI; 3:SPI */ -+ sprd,panel-if-type = <2>; -+ sprd,power-gpio-delay = <20>; -+ sprd,dsi-switch = <1>; -+ -+ /* -+ * LT8912B is a bridge and has no DCS LCD ID register. -+ * Use a dummy panel id so U-Boot passes this panel to kernel. -+ */ -+ sprd,lcd-id-tokernel = <0xffff>; -+ sprd,reset-on-sequence = <1 5>, <0 5>, <1 5>, <0 5>, <1 20>; -+ sprd,reset-off-sequence = <0 20>; -+ sprd,initial-command = [ -+ ]; -+ sprd,sleep-in-command = [ -+ ]; -+ sprd,sleep-out-command = [ -+ ]; -+ -+ display-timings { -+ timing0 { -+ clock-frequency = <153600000>; -+ hactive = <1920>; -+ vactive = <1080>; -+ hfront-porch = <88>; -+ hsync-len = <44>; -+ hback-porch = <148>; -+ vfront-porch = <56>; -+ vsync-len = <6>; -+ vback-porch = <60>; -+ }; -+ }; -+ }; -+ }; -+}; diff --git a/HDMI/LT8912B/LT8912B Ap note.pdf b/HDMI/LT8912B/LT8912B Ap note.pdf deleted file mode 100644 index a37e3b68de539849046501fcd3e1544bfbfddf68..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1320884 zcmdSBXFyZkwkR4!M2aBN5eN!M@4ZGuK)N*PAkus9B`N~ar7H*#={3?jQL0Fj8U*RR zhu%VR7vHz{{@nZSbM8L(z4zk<=E9ZCHRc#|)H%k8EKeROaP#ws60o#Zc8%X85M<$$y^h36kg>)3fZ0@wnJ>$sb{ zx&jaKDwsQZSjouTv~sq*q+aZ=U66BebaB^qHMg*0hJJ zw-x_bLhvsP0FeBb_-ZloUrq=92>kiylI>b1f8p}StiK^6#|JzGfWKT)j{g!VaWP;G_>OUnLvnZE=26X;*d z@C#kO^Y`ojaGBo}=5nKc1N0}*e=H*=d`ZneuK&Yj02KdDjjWP3qxGe{GV(rD12)&i z-O1b$V2v!mBi=u@{89=PwLLF&lGnog_stji3yhqLGa#yfPKyHX0aB@EWoc*r(8c#s zo_?3;C+6Q0 zA8RP+2=Flizkk0GX1tW|KOgv;R$M-#{YZ@QQUw7(m!STn>4~|`ZyI`u^xwFvVCU!w z*aKb#M}Xi*R)6ROud0=^ji)W6py;K75qNk4_Q&Zaf$xXhq(S=-KJu^~Jil-cX?=fn z_XKKc91{og&rxNq49^_tLy0F$HxH>6@GBjrXzg?*6&v;TYQp&}AF%Sr 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