适配新七寸屏

2026-11-09 10:18:46 +08:00
parent a19e595794
commit 7f6fd3bd9d
10 changed files with 131 additions and 126 deletions
@@ -11,7 +11,7 @@
 		sprd,dsi-lane-number = <4>;
 		sprd,dsi-color-format = "rgb888";

-		/* Vendor PLL_CLOCK: 407 Mbps per lane. */
+		/* Last visually verified clean U-Boot configuration. */
 		sprd,phy-bit-clock = <407000>;
 		sprd,phy-escape-clock = <20000>;

@@ -28,7 +28,7 @@
 		sprd,reset-on-sequence = <1 5>, <0 10>, <1 120>;
 		sprd,reset-off-sequence = <0 20>;

-		sprd,use-dcs-write;
+		/* Vendor table entries are 0x23 generic short writes. */
 		sprd,initial-command = [
 			23 00 00 02 E0 00
 			23 00 00 02 E1 93
@@ -241,13 +241,14 @@

 		display-timings {
 			timing0 {
-				clock-frequency = <67750800>;
+				clock-frequency = <64000000>;
 				hactive = <800>;
 				vactive = <1280>;
 				hback-porch = <20>;
 				hfront-porch = <20>;
-				vback-porch = <8>;
-				vfront-porch = <17>;
+				/* Keep the U-Boot-only timing that produced a clean logo. */
+				vback-porch = <24>;
+				vfront-porch = <1>;
 				hsync-len = <20>;
 				vsync-len = <8>;
 			};