diff --git a/arch/arm/cpu/armv8/qogirn6pro/mcu.c b/arch/arm/cpu/armv8/qogirn6pro/mcu.c index 94bff645c..0a16c2f08 100755 --- a/arch/arm/cpu/armv8/qogirn6pro/mcu.c +++ b/arch/arm/cpu/armv8/qogirn6pro/mcu.c @@ -32,6 +32,9 @@ void chipram_env_set(u32 mode) p_env->magic = CHIPRAM_ENV_MAGIC; p_env->mode = mode; p_env->dram_size = 0; +#ifdef CONFIG_SD_CARD_BOOT + p_env->sd_boot = TRUE; +#endif if(BOOTLOADER_MODE_DOWNLOAD == mode) p_env->channel_sel = FDL_GetBootMode(); else @@ -799,6 +802,9 @@ void pll_sel_cfg(void) BIT_PMU_APB_RCO100M_TOP_DVFS_SEL | BIT_PMU_APB_RCO100M_CSYSPWRUPREQ_SEL ; + /* RCO60M select pub to prevent clk_bisr gfree-mux switching failure */ + REG32(REG_PMU_APB_RCO60M_REL_CFG) |= BIT_PMU_APB_RCO60M_PUB_SEL ; + } //avoid situation that mpll pd when the core pd //these bits will be enbale in apcpu_dvfs_hw.c @@ -895,6 +901,10 @@ void config_for_rco100m_solution(void) CHIP_REG_WRITE(REG_AON_CLK_CGM_DEBOUNCE_SEL_CFG, BIT_AON_CLK_CGM_DEBOUNCE_SEL(0x2), BIT_AON_CLK_CGM_DEBOUNCE_SEL(~0)); + + /* bisr logic auto select rco enable */ + REG32(REG_PMU_APB_BISR_CLK_SEL_RCO_CTRL) |= BIT_PMU_APB_BISR_AUTO_SEL_RCO_EN; + /* PAD XTL_EN1 should not mask cm4, uboot will configure this */ /* pll_pd bypass rco */ diff --git a/arch/arm/cpu/armv8/qogirn6pro/ufs_global_reg.c b/arch/arm/cpu/armv8/qogirn6pro/ufs_global_reg.c index 2095b57af..03813341a 100644 --- a/arch/arm/cpu/armv8/qogirn6pro/ufs_global_reg.c +++ b/arch/arm/cpu/armv8/qogirn6pro/ufs_global_reg.c @@ -49,6 +49,7 @@ int ufshci_init_phy() dme_set(ARG1_MIB_SEL(0x8009, 4), 0x1); dme_set(ARG1_MIB_SEL(0x8009, 5), 0x1); dme_set(0xd085, 0x1); + dme_set(0x8114, 0x1); ret = ufs_phy_sram_init_done(); if (ret) diff --git a/arch/arm/include/asm/arch-qogirn6pro/chip_qogirn6pro/redefine.h b/arch/arm/include/asm/arch-qogirn6pro/chip_qogirn6pro/redefine.h index 15122fb76..3d75ca658 100644 --- a/arch/arm/include/asm/arch-qogirn6pro/chip_qogirn6pro/redefine.h +++ b/arch/arm/include/asm/arch-qogirn6pro/chip_qogirn6pro/redefine.h @@ -19,6 +19,14 @@ #define AON_CLK_FREQ_384M 0X02 #define AP_CLK_FREQ_384M 0X03 +/* referenced by sd_driver.c */ +#define REG_BUS_EB REG_AP_AHB_AHB_EB +#define REG_BUS_RST REG_AP_AHB_AHB_RST +#define BIT_BUS_SDIO0_EB BIT_AP_AHB_SDIO0_EB +#define BIT_BUS_SDIO0_SOFT_RST BIT_AP_AHB_SDIO0_SOFT_RST +#define REG_SELECT_SDIO0_CLK_SOURCE REG_AON_CLK_CGM_SDIO0_2X_SEL_CFG +#define BIT_SELECT_SDIO0_390M (0X04) + /* referenced by efuse.c */ #define BIT_EFUSE_SOFT_RST BIT_AON_APB_EFUSE_SOFT_RST #define BIT_EFUSE_EB BIT_AON_APB_AON_EFUSE_EB diff --git a/config.mk b/config.mk index 6c0216397..4d208385b 100755 --- a/config.mk +++ b/config.mk @@ -148,6 +148,9 @@ endif ifeq ($(CONFIG_EMMC_SPL), true) PLATFORM_CPPFLAGS += -DCONFIG_EMMC_BOOT endif +ifeq ($(CONFIG_SD_SPL), true) + PLATFORM_CPPFLAGS += -DCONFIG_SD_CARD_BOOT +endif ifeq ($(CONFIG_NANDC_SPL), true) PLATFORM_CPPFLAGS += -DCONFIG_NAND_BOOT diff --git a/ddr/ddr_init/init/ddrc/r3p1/ddrc_common.h b/ddr/ddr_init/init/ddrc/r3p1/ddrc_common.h index 62e046e1e..99b71e83b 100644 --- a/ddr/ddr_init/init/ddrc/r3p1/ddrc_common.h +++ b/ddr/ddr_init/init/ddrc/r3p1/ddrc_common.h @@ -15,8 +15,9 @@ #ifndef __DDR_COMMON_H #define __DDR_COMMON_H +#include "sprd_maintain.h" + typedef unsigned char u8; -typedef unsigned short u16; typedef unsigned int u32; typedef unsigned long ulong; typedef unsigned long long u64; @@ -34,7 +35,6 @@ typedef char boolean; #define TRUE 1 #define FALSE 0 -#define NULL 0 #define DDR_CLK_26M 26 #define DDR_CLK_156M 156 @@ -107,7 +107,6 @@ typedef enum DRAM_MR_TYPE typedef enum DRAM_TYPE { - DRAM_LP3 = 0x30, DRAM_LP4 = 0x40, DRAM_LP4X = 0x41 }DRAM_TYPE_E; @@ -140,11 +139,11 @@ typedef enum DDR_IO_DS_TYPE void reg_bit_set(u32 addr, u32 start_bit, u32 bits_num, u32 val); u32 reg_bit_get(u32 addr, u32 start_bit, u32 bits_num); void wait_us(u32 us); +void wait_100ns(u32 ns); void dmc_print_str(const char *string); void print_dec(int val); void print_hex(u32 val); void print_string(const char *string); - void dmc_phy_train(u32 ddr_clk, u32 fn); void dmc_mrw(DRAM_MR_TYPE_E mr_num, DRAM_CS_TYPE_E cs_num, u32 mr_data); #endif diff --git a/ddr/ddr_init/init/ddrc/r3p1/ddrc_feature_init.h b/ddr/ddr_init/init/ddrc/r3p1/ddrc_feature_init.h index be80cf297..d2cb9e2c9 100644 --- a/ddr/ddr_init/init/ddrc/r3p1/ddrc_feature_init.h +++ b/ddr/ddr_init/init/ddrc/r3p1/ddrc_feature_init.h @@ -59,6 +59,9 @@ typedef enum INTERLEAVE_SIZE{ }INTERLEAVE_SIZE_E; -void ddrc_ctrl_qos_set(); -void ddrc_ctrl_interleave_set(u32 intlv_size ); +void ddrc_ctrl_qos_set(void); +void ddrc_ctrl_interleave_init(void); +void ddrc_ctrl_interleave_set(u32 intlv_size); +void ddrc_pub_apb_cfg(void); + #endif diff --git a/ddr/ddr_init/init/ddrc/r3p1/ddrc_init.c b/ddr/ddr_init/init/ddrc/r3p1/ddrc_init.c index b6375d9dc..ae9800992 100644 --- a/ddr/ddr_init/init/ddrc/r3p1/ddrc_init.c +++ b/ddr/ddr_init/init/ddrc/r3p1/ddrc_init.c @@ -92,28 +92,28 @@ void dmc_freq_sel_search(u32 ddr_clk, u32* fn) case 768: *fn = 0x2; break; case 533: *fn = 0x1; break; case 384: *fn = 0x0; break; - default: while(1); + default: spl_error_handler(PHASE_DDR_INIT_FREQ_SEL_FAILED); } } -void ddrc_ctrl_soft_reset() +void ddrc_ctrl_soft_reset(void) { //ddrc soft reset reg_bit_set(DMC_SOFT_RST_CTRL, 2, 1, 0x1);//dmc_soft_rst } -void ddrc_ctrl_soft_release() +void ddrc_ctrl_soft_release(void) { reg_bit_set(DMC_SOFT_RST_CTRL, 2, 1, 0x0);//dmc_soft_rst } -void ddrc_phy_soft_reset() +void ddrc_phy_soft_reset(void) { //ddrc phy soft reset reg_bit_set(DMC_SOFT_RST_CTRL, 0, 1, 0x1);//ddrphy_soft_rst } -void ddrc_phy_soft_release() +void ddrc_phy_soft_release(void) { reg_bit_set(DMC_SOFT_RST_CTRL, 0, 1, 0x0);//ddrphy_soft_rst } @@ -199,14 +199,14 @@ void ddrc_clk_cfg(u32 fn) reg_bit_set(DMC_CTL0_(0x012c), 4, 3, fn);//drf_dfs_reg_sel-This fileds select the phy timming parameter } -void ddrc_dmc_lowpower_set() +void ddrc_dmc_lowpower_set(void) { //dmc config reg_bit_set(DMC_CTL0_(0x0000), 8, 1, 0x0);//rf_auto_sleep_en reg_bit_set(DMC_CTL0_(0x0124), 12, 1, 0x0);//drf_ext_clk_ag_en } -void ddrc_ctrl_set() +void ddrc_ctrl_set(void) { //support different dram type reg_bit_set(DMC_CTL0_(0x0100), 8, 1, 0x0);//drf_data_width 0:x16/1:x32 @@ -244,7 +244,7 @@ void ddrc_ctrl_set() reg_bit_set(DMC_CTL0_(0x017c), 24, 6, 0x04);//wbuf_waterlevel1 } -void ddrc_ctrl_timing_fn() +void ddrc_ctrl_timing_fn(void) { u32 fn, i; u32 *pvalue; @@ -274,7 +274,7 @@ void ddrc_ctrl_timing_fn() #endif } -void ddrc_phy_timing_fn() +void ddrc_phy_timing_fn(void) { u32 fn, num; u32 *pvalue; @@ -292,13 +292,13 @@ void ddrc_phy_timing_fn() REG32(DMC_PHY0_(0x00fc + (fn * 0xc0))) = 0x6a; } -void ddrc_phy_set() +void ddrc_phy_set(void) { reg_bit_set(DMC_PHY0_(0x0004), 18, 1, 0x1);//rf_phy_lpddr4_mode reg_bit_set(DMC_PHY1_(0x0004), 18, 1, 0x1);//rf_phy_lpddr4_mode } -void ddrc_ds_odt_set() +void ddrc_ds_odt_set(void) { ddrc_ca_ds_set(DDRC_CA_DS_LP4X); ddrc_dq_ds_set(DDRC_DQ_DS_LP4X); @@ -342,7 +342,7 @@ void ddrc_dbi_set(u32 current_clk) } /*Close dbi for all freq Befor training seq*/ -void ddrc_dbi_close() +void ddrc_dbi_close(void) { u32 fn; for (fn = 0; fn < dram_info.fn_max; fn++) { @@ -355,14 +355,14 @@ void ddrc_dbi_close() } } -void ddrc_auto_refresh_open() +void ddrc_auto_refresh_open(void) { //step3:enable auto refresh reg_bit_set(DMC_CTL0_(0x010c),15, 1,0x1);//auto pre bank refresh reg_bit_set(DMC_CTL0_(0x010c),12, 1,0x1);//drf_auto_ref_en } -void ddrc_master_dll_lock() +void ddrc_master_dll_lock(void) { //bit[31:28] dll lock wait ac0 //bit[26:24] dll pd cnt0 ac0 @@ -397,7 +397,6 @@ void dmc_mrw(DRAM_MR_TYPE_E mr_num,DRAM_CS_TYPE_E cs_num,u32 mr_data) reg_bit_set(DMC_CTL0_(0x0104), 24, 1, 0x1);//dsoft_mrw while(((REG32(DMC_CTL0_(0x0104)) >> 19) & 0x1ff) != 0); - wait_us(1); } @@ -541,7 +540,7 @@ void dram_powerup_seq(u32 fn) lpddr4_powerup_seq(fn); } -void ddrc_dmc_post_set() +void ddrc_dmc_post_set(void) { //step1:enable auto gate&auto sleep reg_bit_set(DMC_CTL0_(0x0000), 8, 2,0x3);//rf_auto_sleep_en @@ -557,7 +556,8 @@ void ddrc_dmc_post_set() reg_bit_set(DMC_CTL0_(0x012c), 0, 4, 0xf);//drf_dfs_en reg_bit_set(DMC_CTL0_(0x012c), 12, 4, 0x5);//enable mrw cnt reg_bit_set(DMC_CTL0_(0x012c), 17, 1, 0x1);//drf_dfs_clk_stop_en - reg_bit_set(DMC_CTL0_(0x012c), 11, 1, 0x0);//PUB sleep with high freq, CKE should be low when dfs + /*cke glitch issue when dfs, so we let cke keep low*/ + reg_bit_set(DMC_CTL0_(0x012c), 11, 1, 0x0);//cke status when dfs //step5:enable auto zqc reg_bit_set(DMC_CTL0_(0x0118), 0, 24, 0x0);//auto zqc en @@ -666,7 +666,7 @@ void ddrc_train_flow(u32 ddr_mode, u32 train_top_clk) if (result) { print_string("bist fail\n"); - while(1); + spl_error_handler(PHASE_DDR_BIST_FAILED); } reg_bit_set(DMC_CTL0_(0x0144), 16, 1, 0x0);//disable ctrl update } @@ -674,13 +674,13 @@ void ddrc_train_flow(u32 ddr_mode, u32 train_top_clk) REG32(PUB_APB_BASE_ADDR + 0x4000 + 0x2000) = 0x1 << 20;//disable pub clk aon to disable dmc phy hclk } -void pub_axi_port_lowpower_close() +void pub_axi_port_lowpower_close(void) { //Disable lowpower mode REG32(DDR_CHN_SLEEP_CTRL0) &= ~(0xff << 8); } -void pub_lowpower_set() +void pub_lowpower_set(void) { //AXI PORT lowpower enable reg_bit_set(DDR_CHN_SLEEP_CTRL0, 8, 8, 0xff); @@ -692,12 +692,12 @@ void pub_lowpower_set() reg_bit_set(DDR_SLP_WAIT_CNT, 0, 16, 0x80); } -void pub_acc_rdy_set() +void pub_acc_rdy_set(void) { REG32(PUB_ACC_RDY) |= (1 << 0); } -void pmu_apb_state_set() +void pmu_apb_state_set(void) { //ddr_phy_cke_ret_en reg_bit_set(DDR_PHY_RET_CFG,0, 1, 0x1); @@ -747,28 +747,28 @@ static int zqc_resutl_check(u32 zq_a, u32 zq_b) if ((zq_a - zq_b) <= 3) { zq_pcal=(zq_a + zq_b) / 2; } else { - dmc_print_str("\r\nP>4"); //del P>4 + dmc_print_str("\r\nP > 4"); return -1; } } else { if ((zq_b - zq_a) <= 3) { zq_pcal = (zq_a + zq_b) / 2; } else { - dmc_print_str("\r\nN>4"); //del N>4 + dmc_print_str("\r\nN > 4"); return -1; } } return zq_pcal; } -void ddrc_lock() +void ddrc_lock(void) { //step8:enable dmc_rf wr lock REG32(DMC_CTL0_(0x009c)) = 0x0; REG32(DMC_PHY0_(0x0ffc)) = 0x0; } -void ddrc_zqc_seq() +void ddrc_zqc_seq(void) { u32 zqcal_flag, zqcal_val_a = 0, zqcal_val_b = 0; int zq_ncal = 0, zq_pcal = 0; @@ -804,7 +804,7 @@ void ddrc_zqc_seq() if (zqcal_val_a == 0x0) { //zq cal fail dmc_print_str("\r\nD P f"); - while(1); + spl_error_handler(PHASE_DDR_INIT_PMOS_FAILED); } } @@ -833,7 +833,7 @@ void ddrc_zqc_seq() dmc_print_str("\r\nI P f"); if (zqcal_val_a == 0xf) dmc_print_str("\r\nnot 240ohm"); - while(1); + spl_error_handler(PHASE_DDR_INIT_PMOS_FAILED); } } } @@ -843,8 +843,8 @@ void ddrc_zqc_seq() #endif zq_pcal = zqc_resutl_check(zqcal_val_a, zqcal_val_b); if (zq_pcal < 0) { - dmc_print_str("\r\nzq P f\n"); //zq pcal fail - while(1); + dmc_print_str("\r\nzq P f\n"); + spl_error_handler(PHASE_DDR_INIT_PMOS_FAILED); } reg_bit_set(DMC_PHY0_(0), 17, 1, 0x0);//rf_zq_cal_pcal_en @@ -868,12 +868,12 @@ void ddrc_zqc_seq() if (zqcal_val_a == 0xf) { //zq cal fail dmc_print_str("I N f"); - while(1); + spl_error_handler(PHASE_DDR_INIT_NMOS_FAILED); } } } #if TEST_DEBUG_LOG_LEVEL > 1 - dmc_print_str("\r\npdio inc dir"); + dmc_print_str("\r\npdio inc dir:"); print_dec(zqcal_val_a); #endif reg_bit_set(DMC_PHY0_(0), 8, 4, 0xf);//rf_zq_cal_pd_sel @@ -893,7 +893,7 @@ void ddrc_zqc_seq() if (zqcal_val_b == 0x0) { //zq cal fail dmc_print_str("\r\nD N f"); - while(1); + spl_error_handler(PHASE_DDR_INIT_NMOS_FAILED); } } } @@ -903,8 +903,8 @@ void ddrc_zqc_seq() #endif zq_ncal = zqc_resutl_check(zqcal_val_a, zqcal_val_b); if (zq_ncal < 0) { - dmc_print_str("\r\nzq N f\n");//zq ncal fail - while(1); + dmc_print_str("\r\nzq N f\n"); + spl_error_handler(PHASE_DDR_INIT_NMOS_FAILED); } reg_bit_set(DMC_PHY0_(0), 18, 1, 0x0);//rf_zq_cal_ncal_en /************End Nmos zq calibration*************/ @@ -971,7 +971,7 @@ static u8 chip_lowv_fail_confirm(void) ret = efuse_read_drv(LOWV_DEFINED_BLOCK_INDEX, LOWV_DEFINED_BLOCK_INDEX, &efuse_block, 1); if (ret != EFUSE_RESULT_SUCCESS) { - print_string("\r\nGet efuse fail");//Get efuse rst fail + print_string("\r\nGet efuse fail"); return EFUSE_FAIL_CHIP; } @@ -1027,7 +1027,7 @@ void ddrc_debug_mode(u32 mode, u32 top_freq) REG32(DDR_REINIT_DEBUG_ADDR + 0x14) = 0x0;//cm4 not use chipram bist para } -void wdg_rst_keep_sre() +void wdg_rst_keep_sre(void) { u32 value; @@ -1051,7 +1051,7 @@ void wdg_rst_keep_sre() } } -void ddrc_reboot_cnt() +void ddrc_reboot_cnt(void) { u32 val=0; if (REG32(DDR_REBOOT_FLAG) != 0x12345678) { @@ -1063,7 +1063,7 @@ void ddrc_reboot_cnt() REG32(DDR_REBOOT_CNT) = val; } #if TEST_DEBUG_LOG_LEVEL>1 - print_string("\r\nRes Time:");//DDR Res Time + print_string("\r\nDDR Reboot Times:"); print_hex(REG32(DDR_REBOOT_CNT)); #endif } @@ -1077,15 +1077,15 @@ void ddrc_target_point_set(u32 target_ddr_clk, u32 train_high_clk) sw_dfs_go(fn_val); #ifndef DDR_SCAN_ENABLE /*target point print*/ - print_string("\r\nddr:"); //ddr target frq + print_string("\r\nddr target freq:"); print_dec(target_ddr_clk); print_string("MHz\n"); #endif } -void ddr_init_pass() +void ddr_init_pass(void) { - print_string("\r\nddr init pass!!!\r\n"); //ddr init pass + print_string("\r\nddr init pass!!!\r\n"); } #ifdef DRAM_TEST @@ -1098,7 +1098,7 @@ void print_tdqs2dq(u32 high_value,u32 low_value,u32 cs_num) high_value = ((high_value << 8) & 0xff00) | (low_value & 0xff); print_string("ch0 cs"); print_dec(cs_num); - print_string(" tdqs2dq="); + print_string(" tdqs2dq ="); value = ((1024 * 1000 * 1000) / (BOOT_FREQ_POINT * high_value)) / 2; print_dec(value); print_string("ps\r\n"); @@ -1126,7 +1126,7 @@ void print_tdqs2dq(u32 high_value,u32 low_value,u32 cs_num) REG32(min_addr) = value; } -void dram_get_tdqs2dq() +void dram_get_tdqs2dq(void) { u32 high_value=0,low_value=0; reg_bit_set(DMC_CTL0_(0x100), 20, 4, 0x1); @@ -1151,7 +1151,7 @@ void dram_get_tdqs2dq() reg_bit_set(DMC_CTL0_(0x100), 20, 4, 0xf); } -void loop_get_tdqs2dq() +void loop_get_tdqs2dq(void) { while (1) { dram_get_tdqs2dq(); @@ -1191,7 +1191,7 @@ void dpll_cfg(u32 clk, u32 pll) *target_ddr_clk:Target DDR frequency *train_high_point :Training Top DDR frequency (according ddr_mode set this variable) ***************************************************************************/ -void sdram_init() +void sdram_init(void) { //dmc_print_str("\r\nSHARKL6pro ddr init...\r\n"); u32 train_high_point = 2133;/*Training High freq point*/ @@ -1211,7 +1211,7 @@ void sdram_init() /*ddr init start*/ #ifndef DDR_SCAN_ENABLE - print_string("ddr init st\r\n"); + print_string("ddr init start!!!\r\n"); #endif #ifdef PUB_DVFS_EN pub_top_dvfs_cfg(); @@ -1325,7 +1325,7 @@ void sdram_init() /*other boot SPECIFIC bist test and reset bist config for retention*/ if (dmc_ddr_test(SCAN_SPECIFIC_ADDR, 0x0, BIST_RESERVE_SIZE - 1)) { dmc_print_str("bist fail\n"); - while(1); + spl_error_handler(PHASE_DDR_BIST_FAILED); } /*pub_sys clk auto gate*/ diff --git a/ddr/ddr_init/init/ddrc/r3p1/ddrc_init.h b/ddr/ddr_init/init/ddrc/r3p1/ddrc_init.h index a7244d119..c3d8ed287 100644 --- a/ddr/ddr_init/init/ddrc/r3p1/ddrc_init.h +++ b/ddr/ddr_init/init/ddrc/r3p1/ddrc_init.h @@ -386,14 +386,11 @@ typedef struct TRAIN_CFG_INFO #define EFUSE_FAIL_CHIP 2 #define LOWV_OR_EFUSE_FAIL_CHIP (1<<1) -#define SML_START 0x3d000000 -#define SML_END (SML_START + 0x00040000) - -#define TOS_START 0x3d040000 -#define TOS_END (TOS_START + 0x03fc0000) - -#define LK_START 0x3f000000 -#define LK_END (LK_START + 0x01000000) +//fix compile warning +void dmc_freq_sel_search(u32 ddr_clk, u32* fn); +void dmc_mrw(DRAM_MR_TYPE_E mr_num,DRAM_CS_TYPE_E cs_num,u32 mr_data); +int dmc_mrr(DRAM_MR_TYPE_E mr_num, DRAM_CS_TYPE_E cs_num, u32* mr_data); +void sdram_init(void); +void sw_dfs_go(u32 fn); #endif - diff --git a/ddr/ddr_init/init/ddrc/r3p1/ddrc_init_train.c b/ddr/ddr_init/init/ddrc/r3p1/ddrc_init_train.c index d4f267ad5..96a9dd9a0 100644 --- a/ddr/ddr_init/init/ddrc/r3p1/ddrc_init_train.c +++ b/ddr/ddr_init/init/ddrc/r3p1/ddrc_init_train.c @@ -14,8 +14,10 @@ #include "ddrc_init.h" #include "dram_support.h" +#include "dram_test.h" #include "ddrc_r3p1_scan_offline.h" /*******************************Training flow*************************************/ + extern DRAM_INFO_T dram_info; extern DDRC_DMC_DTMG_T *dmc_dtmg; extern DDRC_PHY_TMG_T *phy_tmg; @@ -206,9 +208,9 @@ static u32 dmc_phy_train_polling_done(u32 tr_type) //wait train done while (((REG32(DMC_CTL0_(0x0158)) >> (tr_type*4 + 1)) & 0x1) == 0) { #if TEST_DEBUG_LOG_LEVEL > 5 - print_string("not done, wait count:"); + print_string("training not done, wait count:"); print_dec(train_wait_num ++); - print_string("type:"); + print_string("training type:"); print_dec(tr_type); print_string("\r\n"); #endif @@ -216,15 +218,15 @@ static u32 dmc_phy_train_polling_done(u32 tr_type) if ((REG32(DMC_CTL0_(0x0158)) >> (tr_type*4 + 2)) & 0x1) { //dsktraining Failure is not allowed if ((tr_type == 3) || (tr_type == 5)) { - print_string("done but fail"); + print_string("train done but failed "); print_string("type:"); print_dec(tr_type); print_string("\n"); - while(1); + spl_error_handler(PHASE_DDR_TRAINING_NOT_DONE); } } else { #if TEST_DEBUG_LOG_LEVEL > 5 - print_string("done and pass\n"); + print_string("training done and passed!!!\n"); #endif } return 0; @@ -485,7 +487,7 @@ void dmc_phy_train_lp4_cavref_set(u32 vref) //update fsp-wr/op dmc_mrw(DRAM_MR_13, DRAM_CS_ALL, (fsp_op ? 0xc8 : 0x08)); //ca vref setting - dmc_mrw(DRAM_MR_12, DRAM_CS_ALL, vref); //need read compare ,confirm it is ok??/ + dmc_mrw(DRAM_MR_12, DRAM_CS_ALL, vref); //need read compare ,confirm whether it is ok } void dmc_phy_train_lp4_caeye(u32 train_count) @@ -534,23 +536,24 @@ void dmc_phy_train_lp4_caeye(u32 train_count) dmc_phy_train_polling_done(TRAIN_CAEYE_INDEX);//Loop pass_win_temp = (REG32(DMC_CTL0_(0x0168)) & 0x7ff);//bit[10:0]rf train caeye pass window - caeye_value_temp = ((REG32(DMC_CTL0_(0x0168)) >> 11) & 0x7ff);//bit[21:11]:rf train caeye value + caeye_value_temp = ((REG32(DMC_CTL0_(0x0168)) >> 11));//bit[21:11]:rf train caeye value + caeye_value_temp = caeye_value_temp & 0x7ff; #if TEST_DEBUG_LOG_LEVEL>2 print_string("caeye training vref:"); print_hex(vrefca_val); print_string(" "); - print_string("Pass Window Val:"); + print_string("Pass Window Value:"); print_hex(pass_win_temp); print_string(" "); - print_string("Pass Val:"); + print_string("Pass Value:"); print_hex(caeye_value_temp); print_string("\r\n"); if (pass_win_temp < 0x20) { print_string("pw<0x20\r\n"); //reset delay line - while(1); + spl_error_handler(PHASE_DDR_TRAINING_DONE_BUT_FAILED); } #endif if (train_count == 1) {/*Get the highest data and the second highest data for relevant vref*/ @@ -597,7 +600,7 @@ void dmc_phy_train_lp4_caeye(u32 train_count) #endif if (pass_win_max == 0) { print_string("ca pw is 0\n"); - while(1); + spl_error_handler(PHASE_DDR_CAEYE_FAILED); } //set ca eye value-ASIC auto update //reg_bit_set(DMC_PHY0_(dll_ac_ds_addr[train_info.train_chn_num]+train_info.ddr_freq_num*0xc0),0,8,(caeye_value)); @@ -608,11 +611,11 @@ void dmc_phy_train_lp4_caeye(u32 train_count) print_hex(caeye_vref_first1); print_string(" "); print_hex(caeye_vref_last1); - print_string("second range:"); + print_string(" second range:"); print_hex(caeye_vref_first2); print_string(" "); print_hex(caeye_vref_last2); - print_string("CAEYE Vref Val:"); + print_string("CAEYE Vref Value:"); print_hex(train_info.vrefca_val); print_string("\r\n"); #endif @@ -641,7 +644,7 @@ void dmc_phy_train_lp4_caeye(u32 train_count) void dmc_phy_train_lp4_cadsk(void) { u32 val_tmp; - u32 ac0_val, ac1_val; + u32 ac0_val = 0, ac1_val = 0; if (!dmc_phy_train_sel(TRAIN_CADSK_INDEX)) return; @@ -702,10 +705,12 @@ void dmc_phy_train_lp4_cadsk(void) void dmc_phy_train_lp4_rddsk(void) { +#ifdef TRAIN_RDDBI_EN u32 pinmux_dq_in_ds0 = 0; u32 pinmux_dm_in_ds0 = 0; u32 pinmux_dq_in_ds1 = 0; u32 pinmux_dm_in_ds1 = 0; +#endif if (!dmc_phy_train_sel(TRAIN_RDDSK_INDEX)) return; @@ -798,7 +803,7 @@ void dmc_phy_train_lp4_rdeye_cs0(u32 train_count) return; #if TEST_DEBUG_LOG_LEVEL>2 - dmc_print_str("\r\n-------------rdeye train start---------------\r\n"); + dmc_print_str("\r\n-------------rdeye training start---------------\r\n"); #endif // train enable dmc_phy_train_en(TRAIN_RDEYE_INDEX); @@ -863,13 +868,13 @@ void dmc_phy_train_lp4_rdeye_cs0(u32 train_count) print_string("rdeye training vref:"); print_hex(vrefdq_val); print_string(" "); - print_string("Pass Window Val:"); + print_string("Pass Window Value:"); print_hex(REG32(DMC_CTL0_(0x0170))); print_string(" "); - print_string("Pos Pass Val:"); + print_string("Pos Pass Value:"); print_hex(rdeye_pos_value); print_string(" "); - print_string("Neg Pass Val:"); + print_string("Neg Pass Value:"); print_hex(rdeye_neg_value); print_string(" "); //print_string("\r\n"); @@ -913,7 +918,7 @@ void dmc_phy_train_lp4_rdeye_cs0(u32 train_count) #endif if (pass_win_max == 0) { print_string("rd pw is 0\n"); - while(1); + spl_error_handler(PHASE_DDR_RDEYE_FAILED); } /*Deal with training result for delay cells*/ //for (byte_num = 0; byte_num < 4; byte_num++) { @@ -944,7 +949,7 @@ void dmc_phy_train_lp4_rdeye_cs0(u32 train_count) print_string("RDEYE Vref last:"); print_hex(rdeye_vref_last); print_string(" "); - print_string("RDEYE Vref Val:"); + print_string("RDEYE Vref Value:"); print_hex(train_info.vrefdq_rd_val); print_string("\r\n"); #endif @@ -1063,7 +1068,7 @@ void dmc_phy_train_lp4_dqvref_set(u32 vref_val) dmc_mrw(DRAM_MR_14, DRAM_CS_ALL, vref_val); dmc_mrr(DRAM_MR_14, DRAM_CS_ALL, &mr14);//check dq vref setting ok if(((mr14 >> (train_info.train_chn_num*8)) & 0xff) != vref_val) - while(1); + spl_error_handler(PHASE_DDR_VERF_NOT_MATCH); reg_bit_set(DMC_CTL0_(0x0104), 31, 1, 0x0);//dsoft_cmd_allcs off wait_100ns(5); reg_bit_set(DMC_CTL0_(0x0100), 20, 4, 0x3);//dsoft ch sel ch0,1 @@ -1391,7 +1396,7 @@ void dmc_phy_train_lp4_wreye_cs0(u32 train_count) #endif if (pass_win_max == 0) { print_string("wr pw is 0\n"); - while(1); + spl_error_handler(PHASE_DDR_WREYE_FAILED); } //set training result //0x0068,0x007c @@ -1462,7 +1467,9 @@ void dmc_phy_train_lp4_wreye_cs1(void) dmc_phy_train_polling_done(TRAIN_WREYE_INDEX); /*get training result*/ /*[7:0] byte0_pass_window [23:16] byte1_pass_window */ +#ifdef DDR_SCAN_ENABLE pass_win_temp = ((REG32(DMC_CTL0_(0x0170)) >> (train_info.train_chn_num * 16)) & 0xff); +#endif #if TEST_DEBUG_LOG_LEVEL>3 print_string(" "); diff --git a/ddr/ddr_init/init/ddrc/r3p1/ddrc_r3p1_scan_offline.h b/ddr/ddr_init/init/ddrc/r3p1/ddrc_r3p1_scan_offline.h index 895ea83e8..2ecd5195c 100644 --- a/ddr/ddr_init/init/ddrc/r3p1/ddrc_r3p1_scan_offline.h +++ b/ddr/ddr_init/init/ddrc/r3p1/ddrc_r3p1_scan_offline.h @@ -15,6 +15,8 @@ #ifndef __DDR_SCAN_OFFLINE_SPRD_R3P1_H__ #define __DDR_SCAN_OFFLINE_SPRD_R3P1_H__ +#include "ddrc_common.h" + typedef enum { BIST_DS_34OHM = 0, diff --git a/ddr/ddr_init/init/ddrc/r3p1/ddrc_r3p1_scan_offline_eye.c b/ddr/ddr_init/init/ddrc/r3p1/ddrc_r3p1_scan_offline_eye.c index cbba2446a..e14c98316 100644 --- a/ddr/ddr_init/init/ddrc/r3p1/ddrc_r3p1_scan_offline_eye.c +++ b/ddr/ddr_init/init/ddrc/r3p1/ddrc_r3p1_scan_offline_eye.c @@ -23,6 +23,9 @@ extern BIST_INFO bist_info; struct FDL_ChannelHandler *fdl_channel; +extern int regulator_set_voltage(char *p_name, int to_vol); +extern void dmc_phy_train_soft_update_dq(void); +extern void dmc_phy_train_soft_update_ac(void); #define SCAN_SHORT_TIME 0 #define QUAR_DELAY_FREQ DDR_CLK_622M @@ -33,10 +36,6 @@ struct FDL_ChannelHandler *fdl_channel; #define NON_INTERLEAVE_MODE 0 #define DLL_CNT_NUM 6 #define SCAN_RATE 1 - -char* str_trainning_pass_window = "training--> pas window:"; -char* str_raw_win_and_dll_cnt = "raw win&dll cnt:"; - static u64 ddr_size; typedef struct { @@ -108,12 +107,12 @@ u32 rand_u32(){ } */ -void dmc_print_usb(const char *string) +void dmc_print_usb(char *string) { char *s1 = NULL; u32 num = 0; - s1 = (char *)string; + s1 = string; while (*s1 != '\0') { @@ -121,10 +120,10 @@ void dmc_print_usb(const char *string) num++; } s1 = string; - fdl_channel->Write (fdl_channel, s1, num); + fdl_channel->Write (fdl_channel, (const unsigned char *)s1, num); } - +/* static char log_string[33]; static char * toStrDec(u32 val) { @@ -147,7 +146,7 @@ static char * toStrDec(u32 val) static char * toStrHex(u32 val) { - int i, j, num; + int i; u32 temp = val; log_string[0] = '0'; log_string[1] = 'x'; @@ -163,6 +162,7 @@ static char * toStrHex(u32 val) log_string[11] = 0; return log_string; } +*/ /* static int print_dec_Usb(u32 val) { @@ -186,10 +186,10 @@ static int print_hex_Usb(u32 val) */ static void bist_init_scan(u32 bist_chn_num,u64 bist_start_addr,u32 bist_data_mode,u32 write_or_read,u32 bist_size,u8 byte) { - u32 val = 0, i, j; + u32 i, j; volatile u32 offset; u32 bist_start_addr_high; - u64 start_addr; + u64 start_addr = 0; if (bist_chn_num <= 0) bist_chn_num = 1; @@ -229,7 +229,7 @@ static void bist_init_scan(u32 bist_chn_num,u64 bist_start_addr,u32 bist_data_mo REG32(BIST_BASE_ADDR+0x1c+offset) =0x40540540; REG32(BIST_BASE_ADDR+0x20+offset) =0x05405405; REG32(BIST_BASE_ADDR+0x24+offset) =0x54054054; - if(dram_info.dram_type > DRAM_LP3) + if(dram_info.dram_type >= DRAM_LP4) { REG32(BIST_BASE_ADDR+0x28+offset) =0x00550055; REG32(BIST_BASE_ADDR+0x2c+offset) =0x00550055; @@ -257,7 +257,7 @@ static void bist_init_scan(u32 bist_chn_num,u64 bist_start_addr,u32 bist_data_mo REG32(BIST_BASE_ADDR+0x30+i*4+offset) = user_mode_pattern[i]; } break; - default:while(1); + default:spl_error_handler(PHASE_DDR_SCAN_PATTERN_FAILED); } reg_bit_set(BIST_BASE_ADDR+0x00+offset, 3, 2, write_or_read); @@ -276,7 +276,7 @@ static void bist_init_scan(u32 bist_chn_num,u64 bist_start_addr,u32 bist_data_mo #ifdef PERBIT_SCAN /*phy 0 ,1 bit 0 config at the same time*/ - if(dram_info.dram_type > DRAM_LP3) + if(dram_info.dram_type >= DRAM_LP4) { val = ~(bit_mask_num |(bit_mask_num <<16)); } @@ -382,7 +382,7 @@ static u32 get_training_middle(u32 default_cfg_dl_ds,u32 byte,u32 clk,u32 pass_w if(clk > DDR_CLK_1866M) { middle_temp = (middle_temp << 3); middle_temp += ((default_cfg_dl_ds >> 24) & 0x7); - dmc_print_str("mid_vative:"); + dmc_print_str("middle_vative: "); print_hex((middle_temp)); if(write_flag_scan) middle_temp = (middle_temp*regval)/0x80/2; @@ -390,9 +390,9 @@ static u32 get_training_middle(u32 default_cfg_dl_ds,u32 byte,u32 clk,u32 pass_w middle_temp = (middle_temp*regval)/0x40/4; tmp = ((pass_win&0xFF)*regval)/(0x40*4); tmp *= (8/2); - dmc_print_str(str_trainning_pass_window); + dmc_print_str("training--> pass window: "); print_hex((tmp)); - dmc_print_str(str_raw_win_and_dll_cnt); + dmc_print_str("raw win&dll cnt:"); print_hex((pass_win&0xFF)); print_hex(regval); if(middle_temp < tmp) @@ -409,9 +409,9 @@ static u32 get_training_middle(u32 default_cfg_dl_ds,u32 byte,u32 clk,u32 pass_w middle_temp = (middle_temp*regval)/0x80; tmp = ((pass_win&0xFF)*regval)/(0x40*2); tmp *= (8/2); - dmc_print_str(str_trainning_pass_window); + dmc_print_str("training--> pass window: "); print_hex((tmp)); - dmc_print_str(str_raw_win_and_dll_cnt); + dmc_print_str("raw win&dll cnt:"); print_hex((pass_win&0xFF)); print_hex(regval); if(middle_temp < tmp) @@ -434,7 +434,7 @@ static u32 get_training_middle(u32 default_cfg_dl_ds,u32 byte,u32 clk,u32 pass_w { tmp *= 8; } - dmc_print_str(str_trainning_pass_window); + dmc_print_str("training--> pass window: "); print_hex((tmp)); if(middle_temp < tmp) *ps_start = 0; @@ -448,7 +448,7 @@ static u32 get_training_middle(u32 default_cfg_dl_ds,u32 byte,u32 clk,u32 pass_w } void lp4_interleave_en(u32 inter_en) { - if(dram_info.dram_type > DRAM_LP3) + if(dram_info.dram_type >= DRAM_LP4) { if(inter_en==1) { @@ -476,11 +476,11 @@ static void dmc_reg_dump(void) for(j = 0;j < 3;j++) { if(j==0) - dmc_print_str("phy0 reg\r\n"); + dmc_print_str("phy0 reg:\r\n"); else if(j==1) - dmc_print_str("phy1 reg\r\n"); + dmc_print_str("phy1 reg:\r\n"); else - dmc_print_str("dmc reg\r\n"); + dmc_print_str("dmc reg:\r\n"); for(i=0; i<=reg_len[j];) { print_hex(i); @@ -504,16 +504,13 @@ static void scan_pre_set(u32 clk) { u32 regval,i,j; u32 fsp_op; - //u64 size; - //u32 half_mode; - //u32 clk_mode; u32 tmp = 1; - dmc_print_str("\r\nscan ddr type:"); + dmc_print_str("\r\nscan ddr type: "); if(dram_info.dram_type == DRAM_LP4) - dmc_print_str("lp4\r\n"); + dmc_print_str("lpddr4\r\n"); else if(dram_info.dram_type == DRAM_LP4X) - dmc_print_str("lp4x\r\n"); + dmc_print_str("lpddr4x\r\n"); ddr_size = dram_info.cs0_size + dram_info.cs1_size; if(ddr_size > 0x140000000) @@ -525,10 +522,9 @@ static void scan_pre_set(u32 clk) /*enable reg write*/ REG32(DMC_CTL0_(0x009c)) = 0xdeadbeef; -/* - regval = REG32(DMC_PHY_REG_BASE_ADDR + DDR_FREQ_SHIFT + 0x60); - half_mode = (regval >> 2)&0x01; + regval = REG32(DMC_PHY_REG_BASE_ADDR + DDR_FREQ_SHIFT + 0x60); + /*half_mode = (regval >> 2)&0x01; if(regval&(1<<3)) { if(regval&(1<<24)) @@ -538,9 +534,8 @@ static void scan_pre_set(u32 clk) } else clk_mode = 1;//2x -*/ - - dmc_print_str("\r\nrf SCAN RATE:"); + */ + dmc_print_str("\r\nrf SCAN RATE is: "); print_dec(SCAN_RATE); dmc_print_str("\r\nrf phy dll cnt&delay cell(fs):\n"); @@ -586,7 +581,7 @@ static void scan_pre_set(u32 clk) if(clk <= QUAR_DELAY_FREQ) scan_ui /= 4; - dmc_print_str("\r\nscan_ui:"); + dmc_print_str("\r\nscan_ui: "); print_hex(scan_ui); /*disable period cpst and wbuf merge*/ @@ -597,7 +592,7 @@ static void scan_pre_set(u32 clk) reg_bit_set(DMC_CTL0_(0x010c), 12,1,0x0);//drf_auto_self_ref_en lp4_interleave_en(NON_INTERLEAVE_MODE); - if(dram_info.dram_type > DRAM_LP3) + if(dram_info.dram_type >= DRAM_LP4) { fsp_op = reg_bit_get(DMC_CTL0_(0x4e8), 31, 1); reg_bit_set(DMC_CTL0_(0x10c),12,1,0x0);//disable auto refresh @@ -610,9 +605,6 @@ static void scan_pre_set(u32 clk) static void scan_ca_pre_set(int i,u32 vref) { - //u32 regval; - //u64 size; - ddr_size = dram_info.cs0_size + dram_info.cs1_size; REG32(DMC_CTL0_(0x009c)) = 0xdeadbeef; if(ddr_size > 0x140000000) @@ -629,7 +621,7 @@ static void scan_ca_pre_set(int i,u32 vref) reg_bit_set(DMC_CTL0_(0x010c), 12,1,0x0);//drf_auto_self_ref_en lp4_interleave_en(NON_INTERLEAVE_MODE); - if(dram_info.dram_type > DRAM_LP3) + if(dram_info.dram_type >= DRAM_LP4) { //dmc_mrw(DRAM_MR_13, DRAM_CS_ALL, (1 << 3)); //wait_us(5); @@ -652,7 +644,6 @@ static void scan_ca_pre_set(int i,u32 vref) static u64 get_bist_address_lp4(u32 channel_num,u32 rank_num) { - u32 rand32; u64 bist_addr; /*dram_info.cs0_size ->two phy*/ if(channel_num == 0) @@ -677,7 +668,7 @@ static u64 get_bist_address_lp4(u32 channel_num,u32 rank_num) void print_scan_result(u32 rank,u32 byte,u32 shift) { - dmc_print_str("\r\n\r\nscan res->pas window:"); + dmc_print_str("\r\n\r\nscan result--> pass window:"); print_hex(scan_pas_wind); dmc_print_str("mid:"); @@ -695,7 +686,7 @@ void print_scan_result(u32 rank,u32 byte,u32 shift) dmc_print_str(" byte"); print_dec(byte); - dmc_print_str(" train vref scan pas rate:"); + dmc_print_str(" traing vref scan pass rate:"); print_dec(pass_rate); print_dec(eye_mask_pass_rate_high); print_dec(eye_mask_pass_rate_low); @@ -716,7 +707,7 @@ u32 cc = 0; static void check_scan_result(u64 bist_addr,u32 *flag,u32 delay,int *channel,u32 vref,u32 max_delay,u8 byte) { u32 chk_flag; - u32 channel_num,pass_winodw; + u32 pass_winodw; //channel_num = *channel; //bist_addr = get_bist_address_lp4(channel_num, 0); @@ -786,7 +777,7 @@ if(scan_debug == 1){ { pass_winodw = last_pass - first_pass + SCAN_RATE; scan_pas_wind_tmp = pass_winodw; - if((channel !=NULL) && (dram_info.dram_type > DRAM_LP3)) + if((channel !=NULL) && (dram_info.dram_type >= DRAM_LP4)) scan_pas_wind_tmp /= 2; if(pass_winodw > scan_pas_wind) { @@ -818,7 +809,7 @@ static u32 get_pass_rate(u32 pass_wind) tmp = curr_delay_cell*pass_wind; if(ddr_clk > QUAR_DELAY_FREQ) tmp /= 8; - dmc_print_str("pas window(fs):"); + dmc_print_str("pass window(fs):"); print_dec(tmp); //tmp = tmp * SCAN_RATE; /*ui ps*/ @@ -844,7 +835,7 @@ static void check_scan_result_second(u32 ps_start,u32 ps_end,u32 chk_flag,u32 mi /*scan pass winodw*/ pass_rate = get_pass_rate(scan_pas_wind_tmp); - dmc_print_str("\r\nVref:"); + dmc_print_str("\r\nVref: "); print_hex(vref); for(delay = delay_min; delay < delay_max; delay = delay + SCAN_RATE) { @@ -934,18 +925,18 @@ static void set_read_cmos_diff_mode(u32 cmos) { u32 val = 0; - if(dram_info.dram_type > DRAM_LP3) + if(dram_info.dram_type >= DRAM_LP4) val |= (1 << 1); if(cmos == 0) { - dmc_print_str("diff(ib4) mod\r\n"); + dmc_print_str("diff(ib4) mode\r\n"); /*1 ibc vref no change ,ib4 must config for LP4*/ reg_bit_set((DMC_PHY_REG_BASE_ADDR + DDR_FREQ_SHIFT+0xF4), 21, 3, val); reg_bit_set((DMC_PHY_REG_BASE_ADDR+0x1000 + DDR_FREQ_SHIFT+0xF4), 21, 3, val); } else if(cmos == 1) { - dmc_print_str("coms(ibc) mod\r\n"); + dmc_print_str("coms(ibc) mode\r\n"); /*1 ibc vref no change ,ib4 must config for LP4*/ reg_bit_set((DMC_PHY_REG_BASE_ADDR + DDR_FREQ_SHIFT+0xF4), 21, 3, (val | 1)); reg_bit_set((DMC_PHY_REG_BASE_ADDR+0x1000 + DDR_FREQ_SHIFT+0xF4), 21, 3, (val | 1)); @@ -966,7 +957,7 @@ static void perbit_channel_byte_change(int *channel,int *byte) break; } } - if((bit_mask_num >= (1 << 16)) && (dram_info.dram_type > DRAM_LP3)) + if((bit_mask_num >= (1 << 16)) && (dram_info.dram_type >= DRAM_LP4)) bit_mask_num = bit_mask_num >> 16; *byte = k; } @@ -1035,11 +1026,12 @@ static void get_wr_ca_eye_mask_vol_lp4(u32 tmp_default_vref) vref = tmp_default_vref + LP4X_WR_EYE_MASK_VOL_STEP; eye_mask_vol_high = get_wr_ca_vol_shift_lp4(tmp_default_vref,vref); - if(dram_info.dram_type == DRAM_LP4) + if((dram_info.dram_type == DRAM_LP4) && (tmp_default_vref > LP4_WR_EYE_MASK_VOL_STEP)) vref = tmp_default_vref - LP4_WR_EYE_MASK_VOL_STEP; - else + else if((dram_info.dram_type == DRAM_LP4X) + && (tmp_default_vref > LP4X_WR_EYE_MASK_VOL_STEP)) vref = tmp_default_vref - LP4X_WR_EYE_MASK_VOL_STEP; - if(vref < 0) + else vref = 0; eye_mask_vol_low = get_wr_ca_vol_shift_lp4(tmp_default_vref,vref); @@ -1047,13 +1039,12 @@ static void get_wr_ca_eye_mask_vol_lp4(u32 tmp_default_vref) static int scan_write_lp4(int rank_num,u32 clk) { - u32 default_vref,chk_flag,tmp_default_vref; - u32 regval, default_cfg_dl_ds; + u32 default_vref,chk_flag,tmp_default_vref; + u32 default_cfg_dl_ds; int i, j, k=0, vref, delay, max_delay; - u32 middle_temp,reg,reg_diff, ps_start, ps_end, tmp,reg_diff_val; + u32 middle_temp,reg,reg_diff, ps_start, ps_end, reg_diff_val; u32 middle_temp_mod,middle_temp_before_mod; u32 scan_cycle,scan_2cycle; - u32 print_data=0; u64 bist_addr; default_vref = 0; if(clk > QUAR_DELAY_FREQ) @@ -1063,7 +1054,7 @@ static int scan_write_lp4(int rank_num,u32 clk) dmc_mrr(DRAM_MR_14, DRAM_CS_ALL, &default_vref); tmp_default_vref = default_vref; - dmc_print_str("\r\nScan wr st\r\n"); + dmc_print_str("\r\nScan write start\r\n"); for(i = 0;i < DDR_CHANNEL_NUM; i++) { @@ -1080,7 +1071,7 @@ static int scan_write_lp4(int rank_num,u32 clk) } dmc_print_str("\r\nWR PHY"); print_dec(i); - dmc_print_str("B"); + dmc_print_str("BYTE"); print_dec(j); dmc_print_str("bist addr:"); print_hex(bist_addr); @@ -1129,14 +1120,14 @@ static int scan_write_lp4(int rank_num,u32 clk) write_flag = 0xff; get_delay_min_max(rank_num,(2*i + j),middle_temp,max_delay); write_flag = 0; - dmc_print_str("d_min:"); + dmc_print_str("delay_min: "); print_hex(delay_min); - dmc_print_str("d_max:"); + dmc_print_str("delay_max: "); print_hex(delay_max); dmc_print_str("mid:"); print_hex(middle_temp); - dmc_print_str("mid bf mod:"); + dmc_print_str("mid before mod: "); print_hex(middle_temp_before_mod); dmc_print_str("vref:"); @@ -1247,7 +1238,7 @@ static int scan_write_lp4(int rank_num,u32 clk) break; } - dmc_print_str("\r\nScan wr ed\r\n"); + dmc_print_str("\r\nScan write end\r\n"); /*delay at least 500ns for vref update*/ wait_us(1); return 0; @@ -1256,8 +1247,8 @@ static int scan_write_lp4(int rank_num,u32 clk) static int scan_read_lp4(int rank_num,u32 clk,u32 cmos) { u32 default_vref[2],chk_flag; - u32 regval, default_cfg_rd_dl_ds,default_cfg_rd_dl_ds_pos; - int i, j, k, vref, delay,phy_num; + u32 default_cfg_rd_dl_ds,default_cfg_rd_dl_ds_pos; + int i, j, k = 0, vref, delay; u32 middle_temp,reg,reg_pos,ps_start,ps_end,tmp,max_delay; u32 middle_temp_before_mod,middle_temp_mod; u64 bist_addr; @@ -1273,11 +1264,11 @@ static int scan_read_lp4(int rank_num,u32 clk,u32 cmos) default_vref[0] = REG32(DMC_PHY_REG_BASE_ADDR + DDR_FREQ_SHIFT + 0xF4); default_vref[1] = REG32(DMC_PHY_REG_BASE_ADDR+0x1000 + DDR_FREQ_SHIFT + 0xF4); - dmc_print_str("\r\nScan re st\r\n"); + dmc_print_str("\r\nScan read start\r\n"); if(interleave_en == INTERLEAVE_MODE) - dmc_print_str("intlv mode\r\n");//interleave mode + dmc_print_str("interleave mode\r\n"); else - dmc_print_str("non intlv mode\r\n");//interleave mode + dmc_print_str("non interleave mode\r\n"); set_read_cmos_diff_mode(cmos); @@ -1294,9 +1285,9 @@ static int scan_read_lp4(int rank_num,u32 clk,u32 cmos) { j = k%2; } - dmc_print_str("\r\nre PHY"); + dmc_print_str("\r\nread PHY"); print_dec(i); - dmc_print_str(" B"); + dmc_print_str(" byte"); print_dec(j); dmc_print_str("bist addr:"); print_hex(bist_addr); @@ -1306,9 +1297,9 @@ static int scan_read_lp4(int rank_num,u32 clk,u32 cmos) default_cfg_rd_dl_ds = REG32(reg); default_cfg_rd_dl_ds_pos = REG32(reg_pos); - dmc_print_str("dll db0 re neg:"); + dmc_print_str("dll db0 read neg:"); print_hex(default_cfg_rd_dl_ds); - dmc_print_str(" pos:"); + dmc_print_str("dll db0 read pos:"); print_hex(default_cfg_rd_dl_ds_pos); @@ -1322,14 +1313,14 @@ static int scan_read_lp4(int rank_num,u32 clk,u32 cmos) } get_delay_min_max(rank_num,(2*i + j),middle_temp,max_delay); - dmc_print_str("d_min:"); + dmc_print_str("delay_min: "); print_hex(delay_min); - dmc_print_str("d_max:"); + dmc_print_str("delay_max: "); print_hex(delay_max); dmc_print_str("mid:"); print_hex(middle_temp); - dmc_print_str("mid bf mod:"); + dmc_print_str("mid before mod: "); print_hex(middle_temp_before_mod); dmc_print_str("vref:"); @@ -1358,7 +1349,7 @@ static int scan_read_lp4(int rank_num,u32 clk,u32 cmos) for (vref = VREF_PHY_START; vref >= VREF_PHY_END; vref--) #endif { - dmc_print_str("\r\nVref:"); + dmc_print_str("\r\nVref: "); print_hex(vref); /*set read vref*/ @@ -1413,17 +1404,16 @@ scan_debug = i; REG32(DMC_PHY_REG_BASE_ADDR + DDR_FREQ_SHIFT + 0xF4) = default_vref[0]; REG32(DMC_PHY_REG_BASE_ADDR+0x1000 + DDR_FREQ_SHIFT + 0xF4) = default_vref[1]; - dmc_print_str("\r\nScan rd ed\r\n"); + dmc_print_str("\r\nScan read end\r\n"); return 0; } static int scan_ca_lp4(int rank_num,u32 clk) { u32 default_vref,chk_flag; - u32 regval, default_cfg_dl_ac; - int i, vref, delay; - int j = 0; //2byte use same ca/clk - u32 middle_temp,reg,ps_start,ps_end,tmp,max_delay; + u32 default_cfg_dl_ac; + int i, j = 0,vref, delay; + u32 middle_temp,reg,ps_start,ps_end, max_delay; u32 middle_temp_before_mod,middle_temp_mod; u64 bist_addr; @@ -1434,7 +1424,7 @@ static int scan_ca_lp4(int rank_num,u32 clk) max_delay = MAX_DQ_DELAY; dmc_mrr(DRAM_MR_12, DRAM_CS_ALL, &default_vref); - dmc_print_str("\r\nScan CA st\r\n"); + dmc_print_str("\r\nScan CA start\r\n"); for(i = 0;i < DDR_CHANNEL_NUM; i++) { @@ -1446,7 +1436,7 @@ static int scan_ca_lp4(int rank_num,u32 clk) dmc_print_str("\r\nCA PHY"); print_dec(i); - dmc_print_str("bist adr:"); + dmc_print_str("bist addr:"); print_hex(bist_addr); dmc_print_str("cfg_dll_ds_dl:"); print_hex(default_cfg_dl_ac); @@ -1467,14 +1457,14 @@ static int scan_ca_lp4(int rank_num,u32 clk) if(delay_max > max_delay) delay_max = max_delay; } - dmc_print_str("d_min:"); + dmc_print_str("delay_min: "); print_hex(delay_min); - dmc_print_str("d_max:"); + dmc_print_str("delay_max: "); print_hex(delay_max); - dmc_print_str("mid:"); + dmc_print_str("mid: "); print_hex(middle_temp); - dmc_print_str("mid bf mod:"); + dmc_print_str("mid before mod: "); print_hex(middle_temp_before_mod); dmc_print_str("vref:"); @@ -1494,7 +1484,7 @@ static int scan_ca_lp4(int rank_num,u32 clk) if(vref == 0x3F) vref = 0x1D; - dmc_print_str("\r\nVref:"); + dmc_print_str("\r\nVref: "); print_hex(vref); /*set CA vref*/ @@ -1548,12 +1538,12 @@ static int scan_ca_lp4(int rank_num,u32 clk) return 0; } -void print_final_result() +void print_final_result(void) { int i,tmp,j; if(scan_final_result[0] || scan_final_result[1]) { - dmc_print_str("\r\nScan res:\r\n ERR:"); + dmc_print_str("\r\nScan result:\r\n ERROR:"); for(i = 0; i < 2; i++) { if(scan_final_result[i]) @@ -1567,12 +1557,12 @@ void print_final_result() { if(j < SCAN_WR_ITEM_SHIFT) { - dmc_print_str(" read B "); + dmc_print_str(" read byte "); print_dec(j); } else if(j < SCAN_CA_ITEM_SHIFT) { - dmc_print_str(" write B "); + dmc_print_str(" write byte "); print_dec((j -4)); } else @@ -1588,7 +1578,7 @@ void print_final_result() } else { - dmc_print_str("\r\nScan res: ALL PAS"); + dmc_print_str("\r\nScan result: SCAN ALL PASS"); } } @@ -1597,7 +1587,7 @@ static void scan_perbit(int ddr_clk,int scan_item) #ifdef PERBIT_SCAN int j; - dmc_print_str("\r\nperbit st\r\n"); + dmc_print_str("\r\nperbit start\r\n"); for(j = 0;j < 32;j++) { dmc_print_str(string_item[scan_item]); @@ -1611,7 +1601,7 @@ static void scan_perbit(int ddr_clk,int scan_item) scan_write_lp4(0,ddr_clk); } - dmc_print_str("\r\nperbit ed\r\n"); + dmc_print_str("\r\nperbit end\r\n"); bit_mask_num = 0xFFFF; #endif } @@ -1619,10 +1609,7 @@ static void scan_perbit(int ddr_clk,int scan_item) void ddr_scan_offline_r3p1(u32 ddr_clk) { - int i, j, k, cs_num; - u32 vddcore_step[VDDCORE_STEP_CNT]={700, }; - u32 vddmem_step[VDDCORE_STEP_CNT]={0 }; - VOL_SET_FLAG vol_flag; + int i, cs_num; #ifdef SCAN_USB_LOG_ENABLE fdl_channel = FDL_ChannelGet(); @@ -1638,9 +1625,8 @@ void ddr_scan_offline_r3p1(u32 ddr_clk) } #endif pass_win_max_scan_tmp[0] = pass_win_max_scan[0]; + dmc_print_str("\r\nddr scan start\r\n"); pass_win_max_scan_tmp[1] = pass_win_max_scan[1]; - dmc_print_str("\r\nddr scan st\r\n"); - dmc_reg_dump(); cs_num = dram_info.cs_num; @@ -1651,77 +1637,46 @@ void ddr_scan_offline_r3p1(u32 ddr_clk) /*first change vdd core*/ //get_scan_ddr_id(); scan_pre_set(ddr_clk); -#ifdef VDD_CORE_MEM_ADJ - vol_flag = VDD_CORE_SET; - for(j = 0,k = 1; (j < VDDCORE_STEP_CNT)||(k < VDDMEM_STEP_CNT);) + + first_init = 2; + //scan_ca_lp4(0,ddr_clk); + for(i = 0; i < cs_num; i++) { - /*run vdd_core change case*/ - if(vol_flag == VDD_CORE_SET) - { - if(j!=0) - regulator_set_voltage("vddcore",vddcore_step[j]); - j++; - } - /*run vdd_mem change case*/ - if(vol_flag == VDD_MEM_SET) - { - regulator_set_voltage("vddmem",vddmem_step[k]); - k++; - } -#endif + dmc_print_str("\r\nscan cs:"); + print_dec(i); - { - first_init = 2; - //scan_ca_lp4(0,ddr_clk); - for(i = 0; i < cs_num; i++) - { - dmc_print_str("\r\nscan cs:"); - print_dec(i); + /*3 -> use default mode*/ + scan_read_lp4(i,ddr_clk,2); + //scan_read_lp4(0,ddr_clk,0); + //scan_read_lp4(0,ddr_clk,1); + /*use non interleave mode*/ + /* + lp4_interleave_en(INTERLEAVE_MODE); + scan_read_lp4(0,ddr_clk,1); + scan_read_lp4(0,ddr_clk,0); + lp4_interleave_en(NON_INTERLEAVE_MODE); + */ + if(i == 0) + scan_perbit(ddr_clk,SCAN_READ); + } - /*3 -> use default mode*/ - scan_read_lp4(i,ddr_clk,2); - //scan_read_lp4(0,ddr_clk,0); - //scan_read_lp4(0,ddr_clk,1); - /*use non interleave mode*/ - /* - lp4_interleave_en(INTERLEAVE_MODE); - scan_read_lp4(0,ddr_clk,1); - scan_read_lp4(0,ddr_clk,0); - lp4_interleave_en(NON_INTERLEAVE_MODE); - */ - if(i == 0) - scan_perbit(ddr_clk,SCAN_READ); - } - for(i = 0; i < cs_num; i++) - { - dmc_print_str("\r\nscan cs:"); - print_dec(i); - scan_write_lp4(i,ddr_clk); - if(i == 0) - scan_perbit(ddr_clk,SCAN_WRITE); - } + for(i = 0; i < cs_num; i++) + { + dmc_print_str("\r\nscan cs:"); + print_dec(i); + scan_write_lp4(i,ddr_clk); + if(i == 0) + scan_perbit(ddr_clk,SCAN_WRITE); + } #ifdef SCAN_LP4_CA_EANBLE - /*only scan rank 0*/ + /*only scan rank 0*/ //scan_ca_pre_set(0,0x72); - scan_ca_lp4(0,ddr_clk); - //scan_ca_lp4(1,ddr_clk); -#endif - } -#ifdef VDD_CORE_MEM_ADJ - /*restore to default vol*/ - if(j == VDDCORE_STEP_CNT) - { - regulator_set_voltage("vddcore",vddcore_step[0]); - vol_flag = VDD_MEM_SET; - } - if(k == VDDCORE_STEP_CNT) - { - regulator_set_voltage("vddmem",vddmem_step[0]); - } - } + scan_ca_lp4(0,ddr_clk); + //scan_ca_lp4(1,ddr_clk); #endif + print_final_result(); - dmc_print_str("\r\nDDR scan ed\r\n"); + dmc_print_str("\r\nDDR scan end\r\n"); while(1); } diff --git a/ddr/ddr_init/init/ddrc/r3p1/dram_support.c b/ddr/ddr_init/init/ddrc/r3p1/dram_support.c index 67752e158..be9bf61d7 100644 --- a/ddr/ddr_init/init/ddrc/r3p1/dram_support.c +++ b/ddr/ddr_init/init/ddrc/r3p1/dram_support.c @@ -114,7 +114,7 @@ int dram_revision_info_update(u32 cs_num) return 1; } -void dram_byte_latency_mode() +void dram_byte_latency_mode(void) { u32 mr0_val = 0; u32 cs_num; @@ -211,10 +211,9 @@ u32 mr8_to_detect_info(u32 mr8_value, u32 cs_num) return TRUE; } -void dram_type_pinmux_auto_detect() +void dram_type_pinmux_auto_detect(void) { u32 dram_status = 0;//0:emcp 1:discrete - //for bringup fix dram type #if defined(DRAM_TYPE_AUTO_DETECT) int volt_val = 0; @@ -231,9 +230,9 @@ void dram_type_pinmux_auto_detect() dram_status = DRAM_DISCRETE; } else { #if TEST_DEBUG_LOG_LEVEL>1 - print_string("\r\nADC Det Volt err"); + print_string("\r\nADC Detect Volt error!!!"); #endif - while(1); + spl_error_handler(PHASE_DDR_INIT_LP4X_FAILED); } #else dram_info.dram_type = DRAM_TYPE_FIXED; @@ -251,7 +250,7 @@ void dram_type_pinmux_auto_detect() freq_info = (DDRC_FREQ_INFO_T *)(&ddrc_freq_info_lp4[0]); } -void dram_size_dmc_timing_adapter() +void dram_size_dmc_timing_adapter(void) { u32 fn; u32 (*tmg_arr)[8] = lp4_size_timing; @@ -287,7 +286,7 @@ void dram_size_dmc_timing_adapter() } } -void dram_size_ctrl_set() +void dram_size_ctrl_set(void) { u32 col_mode = 0; u32 row_mode = 0; @@ -373,8 +372,8 @@ void dram_size_ctrl_set() col_mode=0x2;cs_position=0x1;cs_mode=0x1; break; default: - print_string("\r\ndet ty fail"); - while(1); + print_string("\r\ndetect type fail!!!"); + spl_error_handler(PHASE_DDR_INIT_SIZE_FAILED); } #else //L5PRO:4GB 2CS X16 @@ -405,7 +404,7 @@ void dram_size_ctrl_set() dram_size_dmc_timing_adapter(); } -void dram_size_auto_detect() +void dram_size_auto_detect(void) { u32 cs_mr8_val = 0; u32 ret; @@ -417,16 +416,16 @@ void dram_size_auto_detect() /********************Detect CS0********************/ ret = dmc_mrr(DRAM_MR_8, DRAM_CS_0, &cs_mr8_val); if (ret) { - print_string("CS0 mr8 read fail\n"); - while(1); + print_string("CS0 mr8 read fail!!!\n"); + spl_error_handler(PHASE_DDR_INIT_MR8_FAILED); } dram_info.mr_reg_cs0 &= ~(0xff << 24); dram_info.mr_reg_cs0 |= (cs_mr8_val << 24); ret = mr8_to_detect_info(cs_mr8_val, DRAM_CS_0);//Caculate DRAM size and update Global variable dram_info.dram_detect_type if (!ret) { - print_string("ddr auto det cs0 fail\n"); - while(1); + print_string("ddr auto detect cs0 fail!!!\n"); + spl_error_handler(PHASE_DDR_INIT_CS_FAILED); } cs_mr8_val=0; @@ -437,7 +436,7 @@ void dram_size_auto_detect() ret = mr8_to_detect_info(cs_mr8_val, DRAM_CS_1); if (!ret) - print_string("ddr auto det cs1 unvalid\n"); + print_string("ddr auto detect cs1 unvalid!!!\n"); /*According above information get dram setting or Manual set dram setting*/ dram_byte_latency_mode(); @@ -452,7 +451,7 @@ void dram_size_auto_detect() print_string("\r\nDRAM CS1 MR8/7/6/5:"); print_hex(dram_info.mr_reg_cs1); } - print_string("\r\nDRAM Type:"); + print_string("\r\nDRAM Type: "); print_hex(dram_info.dram_detect_type); #endif } @@ -536,7 +535,7 @@ void dram_freq_auto_detect(u32* target_fn) #endif } -void ddrc_phy_pinmux_set() +void ddrc_phy_pinmux_set(void) { switch (dram_info.pinmux_type) { case LPDDR4_PINMUX_CASE0: @@ -587,7 +586,7 @@ void ddrc_phy_pinmux_set() REG32(DMC_PHY1_(0x0738)) = 0x87653240;//rf_dq_bit_out_pattern_ds3_31_0 REG32(DMC_PHY1_(0x073c)) = 0x00000017;//rf_dq_bit_out_pattern_ds3_35_32 break; - default: while(1); + default: spl_error_handler(PHASE_DDR_INIT_PINMUX_FAILED); } } diff --git a/ddr/ddr_init/init/ddrc/r3p1/dram_support.h b/ddr/ddr_init/init/ddrc/r3p1/dram_support.h index e9bb2c498..df5082119 100644 --- a/ddr/ddr_init/init/ddrc/r3p1/dram_support.h +++ b/ddr/ddr_init/init/ddrc/r3p1/dram_support.h @@ -86,7 +86,7 @@ typedef enum PCB_DRAM_STATUS { DRAM_EMCP=0, DRAM_DISCRETE -}; +}PCB_DRAM_STATUS_E; typedef enum PINMUX_TYPE { @@ -189,9 +189,13 @@ struct DRAM_TOP_FREQ_SEL #define DRAM_REMAP_ADDR_1 0 #endif -void dram_type_auto_detect(); -void dram_size_auto_detect(); -void ddrc_phy_pinmux_set(); -void dmc_update_param_for_uboot(); +void dram_type_auto_detect(void); +void dram_size_auto_detect(void); +void dram_type_pinmux_auto_detect(void); +void ddrc_phy_pinmux_set(void); +void dmc_update_param_for_uboot(void); +void ddrc_ca_ds_set(u32 ds_val); +void ddrc_dq_ds_set(u32 ds_val); +void dram_freq_auto_detect(u32* target_fn); diff --git a/ddr/ddr_init/init/ddrc/r3p1/dram_test.c b/ddr/ddr_init/init/ddrc/r3p1/dram_test.c index 9bd603f81..147661c77 100755 --- a/ddr/ddr_init/init/ddrc/r3p1/dram_test.c +++ b/ddr/ddr_init/init/ddrc/r3p1/dram_test.c @@ -1,28 +1,20 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Unisoc (Shanghai) Technologies Co., Ltd * SPDX-License-Identifier: LicenseRef-Unisoc-General-1.0 * - * Copyright 2020-2022 Unisoc (Shanghai) Technologies Co., Ltd + * Copyright 2020-2023 Unisoc (Shanghai) Technologies Co., Ltd. + * * Licensed under the Unisoc General Software License, version 1.0 (the License); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * https://www.unisoc.com/en_us/license/UNISOC_GENERAL_LICENSE_V1.0-EN_US + * * Software distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OF ANY KIND, either express or implied. * See the Unisoc General Software License, version 1.0 for more details. - */ - -/************** -**qos configure -**interleave configure -**lowpower -**Self-Refresh -** -** -************/ +*/ + #include "ddrc_init.h" #include "dram_test.h" -#include "dram_support.h" #ifdef DDR_SCAN_ENABLE #define dmc_print_str(x) NULL @@ -33,6 +25,8 @@ extern DRAM_INFO_T dram_info; BIST_INFO bist_info; /**********************Bist*******************************/ u32 bist_data_mode[4] = {FOUR_WORDS, FOUR_WORDS, FOUR_WORDS, FOUR_WORDS}; +//Open this define if you want userpattern define +#ifdef DDR_SCAN_ENABLE u32 user_mode_pattern[]= { BIST_DATA_00_PATTERN, @@ -68,6 +62,9 @@ u32 user_mode_pattern[]= BIST_DATA_30_PATTERN, BIST_DATA_31_PATTERN }; +#else +u32 user_mode_pattern[1]={0}; +#endif u32 sipi_mode_pattern[]= { @@ -88,7 +85,7 @@ u32 lfsr_mode_pattern[] = BIST_DATA_LFSR_SEED_H0, BIST_DATA_LFSR_SEED_H1 }; -void bist_en() +void bist_en(void) { u32 master_bit_set = ((PORT6_PUBCP_AUDCP_EN<<6)| (PORT5_WTLCP_EN<<5)| @@ -103,10 +100,10 @@ void bist_en_single(u8 bist_chn) { reg_bit_set(0x60054000, 23, 1, 0x1); //pub_clk_dmc_bist_eb reg_bit_set(0x60053104, 8, 8, 0x0); //port low power dis - REG32(BIST_PORT_ADDR) = 0x1A; + REG32(BIST_PORT_ADDR) = 0x1A; //bit 0 for bist0,bit 1 for bist1,bit 4 for bist2 } -void bist_dis() +void bist_dis(void) { REG32(BIST_PORT_ADDR) = 0x0; REG32(0x60053104) |= (0xff << 8); //port low power en @@ -277,18 +274,18 @@ void print_bist_fail(u32 bist_chn_num) u32 print_dram_addr = 0x0; volatile u32 offset = bist_chn_num * 0x4000; u32 i = 0; - print_string("\r\nbist fail adr:"); + print_string("\r\nbist fail addr:"); bist_fail_addr = REG32(BIST_BASE_ADDR + 0x00b4 + offset); print_hex(bist_fail_addr); - dmc_print_str("\r\fail:"); + dmc_print_str("\r\nbist fail data:"); for (i = 0; i < 4; i++) { print_hex(REG32(BIST_BASE_ADDR + 0x00b8 + i*0x4 + offset)); - print_string(" "); + print_string(" "); } - dmc_print_str("\r\nexp:"); + dmc_print_str("\r\nbist exp data:"); for(i = 0; i < 4; i++) { print_hex(REG32(BIST_BASE_ADDR + 0x00e0 + i*0x4 + offset)); - print_string(" "); + print_string(" "); } print_string("\n"); //while (1); @@ -362,7 +359,7 @@ void bist_test_entry_chn(u32 bist_chn_num,u32* bist_result) { dmc_print_str("\r\nbist fail"); //print_bist_fail(); - while(1); + spl_error_handler(PHASE_DDR_BIST_TEST_FAILED); }else { dmc_print_str("\r\nbist pass"); @@ -385,19 +382,13 @@ int dram_bist_all_space(u64 except_start, u64 except_end) bist_info.bist_num = 1;//use for bist1 - if (dram_info.cs_num == 2) { + if (dram_info.cs_num == 2) dram_size = dram_info.cs0_size + dram_info.cs1_size; - } else if(dram_info.cs_num == 1) { + else if(dram_info.cs_num == 1) dram_size = dram_info.cs0_size; - } else { -#if TEST_DEBUG_LOG_LEVEL>0 - print_string("err size\n"); -#endif - return -1; - } if (except_start > except_end) { #if TEST_DEBUG_LOG_LEVEL>0 - print_string("Err: except_start > except_end !!"); + print_string("Error:dram_bist_all_space : except_start > except_end !! "); #endif return -1; } @@ -428,18 +419,17 @@ int dram_bist_all_space(u64 except_start, u64 except_end) int ddr_scan_fdl1_test(int start, int end) { - print_string("\r\nScan all ddr space Start!!\r\n"); + print_string("\r\nStart!!\r\n"); print_hex(start); print_hex(end); reg_bit_set(PUB_AUTO_LIGHT_ENABLE,0, 16, 0x0); reg_bit_set(DDR_CHN_SLEEP_CTRL0, 16, 10, 0x0); reg_bit_set(PUB_SMART_LIGHT_ENABLE, 28, 1, 0x0); if (dram_bist_all_space((u64)start, (u64)end)) { - print_string("all bist err\r\n"); - while(1); + print_string("all bist error\r\n"); + spl_error_handler(PHASE_DDR_BIST_ALL_FAILED); } - print_string("\r\nScan all ddr space End!!\r\n"); - dmc_update_param_for_uboot(); + print_string("\r\nEnd!!\r\n"); return 0; } int ddr_selfrefresh_test(u32 timeout) @@ -456,22 +446,16 @@ int dram_bist_specific_space(u64 start_address, u64 end_address) bist_info.bist_mode = BIST_ALLWRC; bist_info.bist_pattern = SIPI_DATA_PATTERN; bist_info.bist_data_mode = bist_data_mode[bist_info.bist_num]; - if (dram_info.cs_num == 2) { + if (dram_info.cs_num == 2) dram_size = dram_info.cs0_size + dram_info.cs1_size; - } else if (dram_info.cs_num == 1) { + else if (dram_info.cs_num == 1) dram_size = dram_info.cs0_size; - } else { -#if TEST_DEBUG_LOG_LEVEL>0 - print_string("err size\n"); -#endif - return 1; - } if ((start_address > end_address) || (start_address > dram_size - 1) || (end_address > dram_size - 1)) { #if TEST_DEBUG_LOG_LEVEL>0 - print_string("Err: start > end or scan address > dram_size\n"); + print_string("Error:dram_bist_specific_space : start > end or scan address > dram_size\n"); #endif return 1; } @@ -502,7 +486,7 @@ int dmc_ddr_test(BIST_SCAN_MODE scan_mode, u64 start, u64 end) ret = dram_bist_specific_space(start, end); return ret; default: - print_string("bist_mode err!\r\n"); + print_string("bist_mode error!!\r\n"); return -1; } return 0; @@ -511,18 +495,7 @@ int dmc_ddr_test(BIST_SCAN_MODE scan_mode, u64 start, u64 end) void rst_normal_all_bist(void) { if (dmc_ddr_test(SCAN_ALL_ADDR, dram_info.cs0_size, dram_info.cs0_size)) { - if (dmc_ddr_test(SCAN_SPECIFIC_ADDR, SML_START, SML_END)) { - print_string("SML"); - while(1); - } - if (dmc_ddr_test(SCAN_SPECIFIC_ADDR, TOS_START, TOS_END)) { - print_string("TOS"); - while(1); - } - if (dmc_ddr_test(SCAN_SPECIFIC_ADDR, LK_START, LK_END)) { - print_string("LK"); - while(1); - } + spl_error_handler(PHASE_DDR_BIST_ALL_FAILED); } } @@ -612,7 +585,7 @@ int test_stuck_address(u32 *bufa, u32 count){ p1 = (u32*) bufa; for(i = 0; i < count; i++, p1++){ if (*p1 != (((j + i) % 2) == 0 ? (u32) p1 : ~((u32) p1))){ - print_string("FAIL: possible bad addr line at phys addr 0x:"); + print_string("FAILURE: possible bad address line at physical address 0x:"); print_hex((u32*)p1); print_string("\n"); while(1); @@ -623,55 +596,55 @@ int test_stuck_address(u32 *bufa, u32 count){ return 0; } -int test_random_value(u32 *bufa, u32 *bufb, u32 count){ - u32 *p1 = bufa; - u32 *p2 = bufb; +int test_random_value(u32 *buf_a, u32 *buf_b, u32 count){ + u32 *p1 = buf_a; + u32 *p2 = buf_b; u32 i; for (i = 0; i < count; i++){ *p1++ = *p2++ = rand_u32(); } - return compare_regions(bufa, bufb, count); + return compare_regions(buf_a, buf_b, count); } -int test_xor_comparison(u32 *bufa, u32 *bufb, u32 count){ - u32 *p1 = bufa; - u32 *p2 = bufb; +int test_xor_comparison(u32 *buf_a, u32 *buf_b, u32 count){ + u32 *p1 = buf_a; + u32 *p2 = buf_b; u32 i; u32 q = rand_u32(); for (i = 0; i < count; i++){ *p1++ ^= q; *p2++ ^= q; } - return compare_regions(bufa, bufb, count); + return compare_regions(buf_a, buf_b, count); } -int test_sub_comparison(u32 *bufa, u32 *bufb, u32 count){ - u32 *p1 = bufa; - u32 *p2 = bufb; +int test_sub_comparison(u32 *buf_a, u32 *buf_b, u32 count){ + u32 *p1 = buf_a; + u32 *p2 = buf_b; u32 i; u32 q = rand_u32(); for (i = 0; i < count; i++){ *p1++ -= q; *p2++ -= q; } - return compare_regions(bufa, bufb, count); + return compare_regions(buf_a, buf_b, count); } -int test_mul_comparison(u32 *bufa, u32 *bufb, u32 count){ - u32 *p1 = bufa; - u32 *p2 = bufb; +int test_mul_comparison(u32 *buf_a, u32 *buf_b, u32 count){ + u32 *p1 = buf_a; + u32 *p2 = buf_b; u32 i; u32 q = rand_u32(); for (i = 0; i < count; i++){ *p1++ *= q; *p2++ *= q; } - return compare_regions(bufa, bufb, count); + return compare_regions(buf_a, buf_b, count); } -int test_div_comparison(u32 *bufa, u32 *bufb, u32 count){ - u32 *p1 = bufa; - u32 *p2 = bufb; +int test_div_comparison(u32 *buf_a, u32 *buf_b, u32 count){ + u32 *p1 = buf_a; + u32 *p2 = buf_b; u32 i; u32 q = rand_u32(); for (i = 0; i < count; i++){ @@ -681,42 +654,42 @@ int test_div_comparison(u32 *bufa, u32 *bufb, u32 count){ *p1++ /= q; *p2++ /= q; } - return compare_regions(bufa, bufb, count); + return compare_regions(buf_a, buf_b, count); } -int test_or_comparison(u32 *bufa, u32 *bufb, u32 count){ - u32 *p1 = bufa; - u32 *p2 = bufb; +int test_or_comparison(u32 *buf_a, u32 *buf_b, u32 count){ + u32 *p1 = buf_a; + u32 *p2 = buf_b; u32 i; u32 q = rand_u32(); for (i = 0; i < count; i++){ *p1++ |= q; *p2++ |= q; } - return compare_regions(bufa, bufb, count); + return compare_regions(buf_a, buf_b, count); } -int test_and_comparison(u32 *bufa, u32 *bufb, u32 count){ - u32 *p1 = bufa; - u32 *p2 = bufb; +int test_and_comparison(u32 *buf_a, u32 *buf_b, u32 count){ + u32 *p1 = buf_a; + u32 *p2 = buf_b; u32 i; u32 q = rand_u32(); for (i = 0; i < count; i++){ *p1++ &= q; *p2++ &= q; } - return compare_regions(bufa, bufb, count); + return compare_regions(buf_a, buf_b, count); } -int test_seqinc_comparison(u32 *bufa, u32 *bufb, u32 count){ - u32 *p1 = bufa; - u32 *p2 = bufb; +int test_seqinc_comparison(u32 *buf_a, u32 *buf_b, u32 count){ + u32 *p1 = buf_a; + u32 *p2 = buf_b; u32 i; u32 q = rand_u32(); for (i = 0; i < count; i++){ *p1++ = *p2++ = (i + q); } - return compare_regions(bufa, bufb, count); + return compare_regions(buf_a, buf_b, count); } int test_solidbits_comparison(u32 *bufa, u32 *bufb, u32 count){ @@ -878,33 +851,56 @@ void ddr_memtester(void){ for (regval=0; ; regval++){ if (!tests[regval].name) break; - switch (regval){ - case 0: - print_string("Rand Val "); - break; - case 1: - print_string("Cmp XOR "); - break; - case 2: - print_string("Cmp SUB "); - break; - case 3: - print_string("Cmp MUL "); - break; - case 4: - print_string("Cmp DIV "); - break; - case 5: - print_string("Cmp OR "); - break; - case 6: - print_string("Cmp AND "); - break; - } if (!tests[regval].fp((u32 *)DST_ADDR, (u32 *)SOURCE_ADDR, MEM_TEST_LEN)){ - print_string("test pass\n"); + switch (regval){ + case 0: + print_string("Random Value "); + break; + case 1: + print_string("Compare XOR "); + break; + case 2: + print_string("Compare SUB "); + break; + case 3: + print_string("Compare MUL "); + break; + case 4: + print_string("Compare DIV "); + break; + case 5: + print_string("Compare OR "); + break; + case 6: + print_string("Compare AND "); + break; + } + print_string(" test pass\n"); }else{ - print_string("test fail\n"); + switch (regval){ + case 0: + print_string("Random Value "); + break; + case 1: + print_string("Compare XOR "); + break; + case 2: + print_string("Compare SUB "); + break; + case 3: + print_string("Compare MUL "); + break; + case 4: + print_string("Compare DIV "); + break; + case 5: + print_string("Compare OR "); + break; + case 6: + print_string("Compare AND "); + break; + } + print_string(" test failed\n"); while(1); } } @@ -921,7 +917,7 @@ void ddr_mem_test(void){ sprd_memcpy((void*)(DST_ADDR + i), (void*)(SOURCE_ADDR + i), 1024); regval = sprd_memcmp((void*)(SOURCE_ADDR + i), (void*)(DST_ADDR + i),1024); if (regval){ - dmc_print_str("lit ddr cp fail\n"); + dmc_print_str("little ddr copy failed\n"); while(1); }else{ //print_string("ddr copy pass\n"); @@ -929,10 +925,10 @@ void ddr_mem_test(void){ } regval = sprd_memcmp((void*)(SOURCE_ADDR), (void*)(DST_ADDR),MEM_TEST_LEN); if(regval){ - print_string("big ddr cmp fail\n"); + print_string("big ddr cmp failed\n"); while(1); }else{ - print_string("big mem cmp pas\n"); + print_string("big mem cmp pass\n"); } } diff --git a/ddr/ddr_init/init/ddrc/r3p1/dram_test.h b/ddr/ddr_init/init/ddrc/r3p1/dram_test.h index 338b34ae7..a29ca3eac 100755 --- a/ddr/ddr_init/init/ddrc/r3p1/dram_test.h +++ b/ddr/ddr_init/init/ddrc/r3p1/dram_test.h @@ -156,15 +156,17 @@ typedef struct /* Function declaration. */ void bist_test_entry_chn(u32 bist_chn_num,u32* bist_result); +void bist_clear(u32 bist_chn_num); +int dmc_ddr_test(BIST_SCAN_MODE scan_mode, u64 start, u64 end); int test_stuck_address(unsigned int *bufa, unsigned int count); -int test_random_value(unsigned int *bufa, unsigned int *bufb, unsigned int count); -int test_xor_comparison(unsigned int *bufa, unsigned int *bufb, unsigned int count); -int test_sub_comparison(unsigned int *bufa, unsigned int *bufb, unsigned int count); -int test_mul_comparison(unsigned int *bufa, unsigned int *bufb, unsigned int count); -int test_div_comparison(unsigned int *bufa, unsigned int *bufb, unsigned int count); -int test_or_comparison(unsigned int *bufa, unsigned int *bufb, unsigned int count); -int test_and_comparison(unsigned int *bufa, unsigned int *bufb, unsigned int count); -int test_seqinc_comparison(unsigned int *bufa, unsigned int *bufb, unsigned int count); +int test_random_value(unsigned int *buf_a, unsigned int *buf_b, unsigned int count); +int test_xor_comparison(unsigned int *buf_a, unsigned int *buf_b, unsigned int count); +int test_sub_comparison(unsigned int *buf_a, unsigned int *buf_b, unsigned int count); +int test_mul_comparison(unsigned int *buf_a, unsigned int *buf_b, unsigned int count); +int test_div_comparison(unsigned int *buf_a, unsigned int *buf_b, unsigned int count); +int test_or_comparison(unsigned int *buf_a, unsigned int *buf_b, unsigned int count); +int test_and_comparison(unsigned int *buf_a, unsigned int *buf_b, unsigned int count); +int test_seqinc_comparison(unsigned int *buf_a, unsigned int *buf_b, unsigned int count); int test_solidbits_comparison(unsigned int *bufa, unsigned int *bufb, unsigned int count); int test_checkerboard_comparison(unsigned int *bufa, unsigned int *bufb, unsigned int count); int test_blockseq_comparison(unsigned int *bufa, unsigned int *bufb, unsigned int count); @@ -174,7 +176,7 @@ int test_bitspread_comparison(unsigned int *bufa, unsigned int *bufb, unsigned i int test_bitflip_comparison(unsigned int *bufa, unsigned int *bufb, unsigned int count); void ddr_memtester(void); void ddr_mem_test(void); -void dram_bist_test(); +void dram_bist_test(void); void dram_mem_test(u32 src_addr,u32 dst_addr); void rst_normal_all_bist(void); diff --git a/drivers/mmc/mmc_v40.c b/drivers/mmc/mmc_v40.c index ee9b944c6..6c3c330b2 100644 --- a/drivers/mmc/mmc_v40.c +++ b/drivers/mmc/mmc_v40.c @@ -1421,6 +1421,11 @@ static BOOLEAN CARD_SDIO_InitCard(SDIO_Hd_Ptr pHd, if(0 != (rspBuf[0] & BIT_7)) { + if (rspBuf[0] & BIT_6) + pHd->high_capacity = TRUE; + else + pHd->high_capacity = FALSE; + break; } @@ -1595,8 +1600,10 @@ static BOOLEAN CARD_SDIO_ReadMultiBlock(CARD_Partition_e cardPartiton, uint32 addr = 0xFFFFFFFF; DATA_Param_t data; - //addr = startBlk*pHd->block_len; - addr = startBlk; + if (pHd->high_capacity) + addr = startBlk; + else + addr = startBlk * pHd->block_len; data.blk_len = pHd->block_len; data.blk_num = num; @@ -1660,7 +1667,11 @@ static BOOLEAN CARD_SDIO_WriteMultiBlock( uint32 addr = 0xFFFFFFFF; DATA_Param_t data; - addr = startBlk; + if (pHd->high_capacity) + addr = startBlk; + else + addr = startBlk * pHd->block_len; + data.blk_len = pHd->block_len; data.blk_num = num; data.data_buf = buf; diff --git a/drivers/mmc/sdio_reg_r8p0.h b/drivers/mmc/sdio_reg_r8p0.h index a39c92523..5da399b0e 100644 --- a/drivers/mmc/sdio_reg_r8p0.h +++ b/drivers/mmc/sdio_reg_r8p0.h @@ -215,6 +215,7 @@ typedef struct SDIO_BusWidth_e bus_width; /* card used bus width */ uint32 block_len; /* card block length */ CARD_Partition_e cur_partition; /* card current partition */ + BOOLEAN high_capacity; /* High Capacity Support */ } SDIO_Handle_t, *SDIO_Hd_Ptr; /************************** cmd info *********************************/ diff --git a/drivers/power/sc27xx_regulator.c b/drivers/power/sc27xx_regulator.c index b258c908c..137ab60ba 100755 --- a/drivers/power/sc27xx_regulator.c +++ b/drivers/power/sc27xx_regulator.c @@ -328,8 +328,10 @@ int regulator_init() ); ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE, BIT_PWR_WR_PROT_VALUE(WR_UNLOCK)); ANA_REG_SET(ANA_REG_GLB_DCDC_WR_PROT_VALUE, BIT_DCDC_WR_PROT_VALUE(DCDC_WR_UNLOCK)); +#ifndef CONFIG_SD_CARD_BOOT ANA_REG_OR(ANA_REG_GLB_LDO_VDDSDCORE_REG0, BIT_LDO_VDDSDCORE_PD); ANA_REG_OR(ANA_REG_GLB_LDO_VDDSDIO_REG0, BIT_LDO_VDDSDIO_PD); +#endif #ifdef CONFIG_ADIE_UMP9621 u32 adie_id = 0; diff --git a/drivers/sd/sd_driver.c b/drivers/sd/sd_driver.c index 279554fc2..fb27600c7 100755 --- a/drivers/sd/sd_driver.c +++ b/drivers/sd/sd_driver.c @@ -964,6 +964,10 @@ static BOOLEAN SD_CARD_SDIO_WriteMultiBlock(SDIO_Hd_Ptr pHd, uint32 startBlk, ui return FALSE; } + if (0 != SDIO_SendCmd(pHd, CARD_CMD12_STOP_TRANSMISSION, NULL, NULL, rspBuf)) { + return FALSE; + } + return TRUE; } diff --git a/drivers/sd/sdio_reg.h b/drivers/sd/sdio_reg.h index d821afec8..1c9092549 100755 --- a/drivers/sd/sdio_reg.h +++ b/drivers/sd/sdio_reg.h @@ -334,7 +334,7 @@ static const CARD_CmdCtlFlg_t s_cmdDetail[] = { {CARD_ACMD55_APP_CMD ,55 ,NULL | CARD_SDIO_R1 |NULL ,NULL}, {CARD_CMD8_IF_COND_MMC ,8 ,SIG_TRANS_CMP | CARD_SDIO_R1 |ERR_DATA_END | ERR_DATA_CRC | ERR_DATA_TIMEOUT , TRANS_MODE_READ | TRANS_MODE_DMA_EN | CMD_HAVE_DATA}, #ifdef CONFIG_SUPPORT_FLASH_WRITE - {CARD_CMD25_WRITE_MULTIPLE_BLOCK, 25 ,SIG_TRANS_CMP | CARD_SDIO_R1 |ERR_DATA_END | ERR_DATA_CRC | ERR_DATA_TIMEOUT ,TRANS_MODE_MULTI_BLOCK | TRANS_MODE_AUTO_CMD23_EN | TRANS_MODE_BLOCK_COUNT_EN | TRANS_MODE_DMA_EN | CMD_HAVE_DATA}, + {CARD_CMD25_WRITE_MULTIPLE_BLOCK, 25 ,SIG_TRANS_CMP | CARD_SDIO_R1 |ERR_DATA_END | ERR_DATA_CRC | ERR_DATA_TIMEOUT ,TRANS_MODE_MULTI_BLOCK | TRANS_MODE_BLOCK_COUNT_EN | TRANS_MODE_DMA_EN | CMD_HAVE_DATA}, #endif {CARD_CMDMAX ,0 ,NULL | CARD_SDIO_NO_RSP |NULL ,NULL} }; diff --git a/drivers/ufs/sprd_ufs.c b/drivers/ufs/sprd_ufs.c index d59a82a27..be2b19991 100644 --- a/drivers/ufs/sprd_ufs.c +++ b/drivers/ufs/sprd_ufs.c @@ -769,53 +769,60 @@ int init_ufs_device() } +int check_pwr_mode_cnt = 0; + void change_ufs_power_mode(void) { int ret = 0; int retry = 100; uint32_t upms_intr_res = 0; - struct ufs_pa_layer_attr pwr_info; - - pwr_info.pwr_rx = FAST_MODE; - pwr_info.pwr_tx = FAST_MODE; - pwr_info.hs_rate = PA_HS_MODE_A; + struct ufs_pa_layer_attr pwr_info = {0}; - /* Get max power mode */ + /* Set max power mode */ #ifdef CONFIG_FPGA pwr_info.lane_rx = 1; pwr_info.lane_tx = 1; + pwr_info.gear_rx = 1; + pwr_info.gear_tx = 1; + pwr_info.pwr_rx = FAST_MODE; + pwr_info.pwr_tx = FAST_MODE; + pwr_info.hs_rate = PA_HS_MODE_A; + if (check_pwr_mode_cnt > 0) + return; #else pwr_info.lane_rx = dme_get(PA_CONNECTEDRXDATALANES); pwr_info.lane_tx = dme_get(PA_CONNECTEDTXDATALANES); -#endif - if (0 == pwr_info.lane_rx || 0 == pwr_info.lane_tx) { + if (check_pwr_mode_cnt == 0) { + pwr_info.pwr_rx = FAST_MODE; + pwr_info.pwr_tx = FAST_MODE; + pwr_info.hs_rate = PA_HS_MODE_B; + pwr_info.gear_rx = dme_get(PA_MAXRXHSGEAR); + pwr_info.gear_tx = dme_peer_get(PA_MAXRXHSGEAR); + } else if (check_pwr_mode_cnt == 1) { + pwr_info.pwr_rx = FAST_MODE; + pwr_info.pwr_tx = FAST_MODE; + pwr_info.hs_rate = PA_HS_MODE_A; + pwr_info.gear_rx = dme_get(PA_MAXRXHSGEAR); + pwr_info.gear_tx = dme_peer_get(PA_MAXRXHSGEAR); + } else if (check_pwr_mode_cnt == 2) { + pwr_info.pwr_rx = SLOW_MODE; + pwr_info.pwr_tx = SLOW_MODE; + pwr_info.gear_rx = 1; + pwr_info.gear_tx = 1; + } else return; - } -#ifdef CONFIG_FPGA - pwr_info.gear_rx = 1; -#else - pwr_info.gear_rx = UFS_HS_G2; -#endif - if (0 == pwr_info.gear_rx) { - pwr_info.gear_rx = dme_get(PA_MAXRXPWMGEAR); - if (0 == pwr_info.gear_rx) { - return; - } - pwr_info.pwr_rx = SLOWAUTO_MODE; - } -#ifdef CONFIG_FPGA - pwr_info.gear_tx = 1; -#else - pwr_info.gear_tx = UFS_HS_G2; #endif - if (0 == pwr_info.gear_tx) { - pwr_info.gear_tx = dme_peer_get(PA_MAXRXPWMGEAR); - if (0 == pwr_info.gear_tx) { - return; - } - pwr_info.pwr_tx = SLOWAUTO_MODE; + + if (0 == pwr_info.lane_rx || 0 == pwr_info.lane_tx) + goto out; + else if ((pwr_info.lane_rx + pwr_info.lane_tx) == 3) { + pwr_info.lane_rx = 1; + pwr_info.lane_tx = 1; } + if ((0 == pwr_info.gear_rx) || (0 == pwr_info.gear_tx) || (pwr_info.gear_rx != pwr_info.gear_tx )) + goto out; + /* Set power mode */ dme_set(PA_TXGEAR, pwr_info.gear_tx); dme_set(PA_RXGEAR, pwr_info.gear_rx); @@ -853,15 +860,24 @@ void change_ufs_power_mode(void) } if (0 == retry) { - return; + goto out; } - ret = (ufs_readl(DW_UFS_HCS) >> 8) & 0x7; + if (1 != ((ufs_readl(DW_UFS_HCS) >> 8) & 0x7)) + goto out; + return; +out: + if (check_pwr_mode_cnt < 2) { +#ifndef CONFIG_SOC_QOGIRL6 + ++check_pwr_mode_cnt; +#endif + ++check_pwr_mode_cnt; + reset_and_restore_hc(); + } return; } - int ufs_init() { ufs_info.base_addr = SPRD_UFS_HCI_BASE; diff --git a/include/configs/uis7885_2h10.h b/include/configs/uis7885_2h10.h index a6914b32d..e778d4c35 100755 --- a/include/configs/uis7885_2h10.h +++ b/include/configs/uis7885_2h10.h @@ -16,12 +16,20 @@ #include #include +#ifdef CONFIG_SD_CARD_BOOT #ifdef CONFIG_UFS_BOOT #ifdef CONFIG_EMMC_BOOT #undef CONFIG_EMMC_BOOT #endif +#undef CONFIG_UFS_BOOT +#endif +#else +#ifdef CONFIG_UFS_BOOT +#ifdef CONFIG_EMMC_BOOT +#undef CONFIG_EMMC_BOOT +#endif +#endif #endif - #define CONFIG_LOAD_TOS_ALONE 1 #define CONFIG_TEECFG_CUSTOM 1 #define CONFIG_TEECFG_LDADDR_START 0xbd040000 @@ -172,8 +180,12 @@ ((CONFIG_SYS_NAND_U_BOOT_SIZE + EMMC_SECTOR_SIZE - 1) / EMMC_SECTOR_SIZE) #endif -#ifdef CONFIG_SD_BOOT +#ifdef CONFIG_SD_CARD_BOOT #define SDCARD_BOOT_SECTOR 200 +#define CONFIG_EFI_PARTITION +#define SD_SECTOR_SIZE 512 +#define CONFIG_UBOOT_MAX_SIZE 0x300000 +#define SML_LOAD_MAX_SIZE (1024*1024) #endif #ifdef CONFIG_UFS_BOOT @@ -258,7 +270,7 @@ #define LOG_RESERVED_ADDR 0xbbe80000 #endif -#define CONFIG_SUPPORT_SPL_MAINTAIN +//#define CONFIG_SUPPORT_SPL_MAINTAIN #ifdef CONFIG_SUPPORT_SPL_MAINTAIN #define CONFIG_SUPPORT_FLASH_WRITE #endif diff --git a/include/sprd_chipram_env.h b/include/sprd_chipram_env.h index dd6746667..2211da30f 100755 --- a/include/sprd_chipram_env.h +++ b/include/sprd_chipram_env.h @@ -42,6 +42,7 @@ typedef struct chipram_env { u32 spl_adjust_flag; u32 spl_edit_flag; //CONFIG_SPL_DOUBLE_SLOT u32 dual_spl_flag; //CONFIG_SPL_DOUBLE_SLOT + u32 sd_boot; #ifdef CONFIG_NAND_BOOT u32 nand_param_trasmit_flag; struct bootloader_header bl_header; diff --git a/nand_spl/emmc_boot.c b/nand_spl/emmc_boot.c index e645ed9be..e4d40444d 100755 --- a/nand_spl/emmc_boot.c +++ b/nand_spl/emmc_boot.c @@ -357,7 +357,8 @@ int write_common_partition(uchar * partition_name,uint32_t size, uint32_t offset #ifdef CONFIG_DUAL_SPL int Hash_Check(void)///add the hash_check { - uboot_size_no_hash=((*(uboot_size_no_hash_addr+BYTE3))<<24)|((*(uboot_size_no_hash_addr+BYTE2))<<16)|((*(uboot_size_no_hash_addr+BYTE1))<<8)|(*(uboot_size_no_hash_addr+BYTE0)); + uboot_size_no_hash=((*(uboot_size_no_hash_addr+BYTE3))<<24)|((*(uboot_size_no_hash_addr+BYTE2))<<16)| + ((*(uboot_size_no_hash_addr+BYTE1))<<8)|(*(uboot_size_no_hash_addr+BYTE0)); sha256_csum_wd(uboot_start_addr,uboot_size_no_hash,hash_temp,NULL); if(0==sprd_memcmp(uboot_start_hash_addr+UBOOT_HASH_SIZE_OFFSET,hash_temp,HASH_TEMP_LEN)) return 0; @@ -452,54 +453,6 @@ int8_t check_sprd_sysdump_sec() } } - -#ifdef CONFIG_MOBILEVISOR -int8_t bootmode_check_sysdump() -{ - uint32 reg_rst_moitor; - uint32 wdt_temp; - uint32 src_flag; - - //step1: check if hw wdt rst pending - ANA_REG_OR(ANA_REG_GLB_ARM_MODULE_EN, BIT_ANA_WDG_EN); //WDG enable - ANA_REG_OR(ANA_REG_GLB_RTC_CLK_EN, BIT_RTC_WDG_EN); //WDG Rtc enable - - wdt_temp = ANA_REG_GET(ANA_WDG_BASE+0x10); //WDG_INT_RAW - wdt_temp &= 0x8; //bit3:wdg_rst_raw - /* don't clear rst/int bit, uboot will read again */ - - //step2: read sc2731 RST_MONITOR reg, 0x2E8 - reg_rst_moitor = ANA_REG_GET(ANA_REG_GLB_POR_RST_MONITOR); - - if(! (reg_rst_moitor & HWRST_STATUS_SYSDUMPEN)) - return 0; - - reg_rst_moitor &= 0xFF; - - //setp3: return status by HWRST - if (wdt_temp) { //hw wdt rst pending - if ( (reg_rst_moitor==HWRST_STATUS_SPECIAL) || (reg_rst_moitor==HWRST_STATUS_PANIC) || (reg_rst_moitor==HWRST_STATUS_NORMAL2) ) { - return 1; - } else if ((reg_rst_moitor==HWRST_MOBILEVISOR) || (reg_rst_moitor==HWRST_SECURITY)) { - return 1; - } else { - return 0; - } - } - - //step4: 7s reset or ext pin - src_flag = ANA_REG_GET(ANA_REG_GLB_POR_SRC_FLAG); //0x2F4 - src_flag &= 0xFFFF; - if ( (src_flag&0x800) || ((src_flag&0x1080) == 0x1000) ) { //7s reset - return 1; - } else if (reg_rst_moitor==HWRST_STATUS_NORMAL2) { - return 1; - } else { - return 0; - } -} -#endif - #define PART_INDEX 0 #if defined(AB_PARTITIONS) || defined(CONFIG_ANDROID_AB) static const char tos_part[][16] = { @@ -648,7 +601,8 @@ static void jump_to_uboot(int i) { __attribute__ ((noreturn)) void (*uboot) (unsigned long, unsigned long); - load_partition_with_header(uboot_part[PART_INDEX + i],CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST,(sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - KEY_INFO_SIZ)); + load_partition_with_header(uboot_part[PART_INDEX + i],CONFIG_UBOOT_MAX_SIZE, + CONFIG_SYS_NAND_U_BOOT_DST,(sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - KEY_INFO_SIZ)); chipram_env_set(BOOTLOADER_MODE_LOAD); spl_phase_trace(PHASE_JUMP_TO_BOOTLOADER); spl_save_trace_flag(); @@ -771,14 +725,17 @@ void nand_boot(void) #endif #if CONFIG_SMLBOOT// whale - load_partition_with_header(sml_part[PART_INDEX + i], SML_LOAD_MAX_SIZE,sml_ldaddr_start,(sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); - load_trustos_with_header(tos_part[PART_INDEX + i], TOS_LOAD_MAX_SIZE,tos_ldaddr_start,(sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); + load_partition_with_header(sml_part[PART_INDEX + i], SML_LOAD_MAX_SIZE, + sml_ldaddr_start,(sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); + load_trustos_with_header(tos_part[PART_INDEX + i], TOS_LOAD_MAX_SIZE, + tos_ldaddr_start,(sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); #endif if (!sysdump_security) { //sysdump mode (tos panic) don't load tos and sml #ifdef CONFIG_TEECFG_CUSTOM spl_phase_trace(PHASE_LOAD_TEE_IMG); - load_partition_with_header(teecfg_part[PART_INDEX + i], TEECFG_LOAD_MAX_SIZE, CONFIG_TEECFG_LDADDR_START, (sys_img_header *)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE)); + load_partition_with_header(teecfg_part[PART_INDEX + i], TEECFG_LOAD_MAX_SIZE, + CONFIG_TEECFG_LDADDR_START, (sys_img_header *)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE)); #ifdef CONFIG_SECBOOT if (SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN, (CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE), NULL, NULL, SECURE_BOOT))) { @@ -790,7 +747,8 @@ void nand_boot(void) #else #if !defined(AB_PARTITIONS) && !defined(CONFIG_ANDROID_AB) /***secboot teecfg dual_backup***/ - load_partition_with_header("teecfg_bak", TEECFG_LOAD_MAX_SIZE, CONFIG_TEECFG_LDADDR_START, (sys_img_header*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE)); + load_partition_with_header("teecfg_bak", TEECFG_LOAD_MAX_SIZE, CONFIG_TEECFG_LDADDR_START, + (sys_img_header*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE)); if (SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN, (CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE), NULL, NULL, SECURE_BOOT))) { spl_error_handler(PHASE_TEE_SV_FAILED); } @@ -800,7 +758,8 @@ void nand_boot(void) #else #if defined(CONFIG_DUAL_BACKUP) && defined(CONFIG_SMLBOOT) if (0 != sprd_hash_check((uint8_t*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE))) { - load_partition_with_header("teecfg_bak", TEECFG_LOAD_MAX_SIZE, CONFIG_TEECFG_LDADDR_START, (sys_img_header*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE)); + load_partition_with_header("teecfg_bak", TEECFG_LOAD_MAX_SIZE, CONFIG_TEECFG_LDADDR_START, + (sys_img_header*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE)); if (0 != sprd_hash_check((uint8_t*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE))) { spl_error_handler(PHASE_TEE_HASH_CHECK_FAILED); } @@ -820,51 +779,25 @@ void nand_boot(void) #endif #ifdef CONFIG_LOAD_ATF - load_partition_with_header(sml_part[PART_INDEX + i], SML_LOAD_MAX_SIZE,sml_ldaddr_start,(sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); + load_partition_with_header(sml_part[PART_INDEX + i], SML_LOAD_MAX_SIZE, + sml_ldaddr_start,(sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); #endif #ifdef CONFIG_LOAD_TOS_ALONE - load_trustos_with_header(tos_part[PART_INDEX + i], TOS_LOAD_MAX_SIZE,tos_ldaddr_start,(sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); + load_trustos_with_header(tos_part[PART_INDEX + i], TOS_LOAD_MAX_SIZE, + tos_ldaddr_start,(sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); #endif } spl_phase_trace(PHASE_LOAD_BOOTLOADER); - load_partition_with_header(uboot_part[PART_INDEX + i],CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST,(sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - KEY_INFO_SIZ)); - -#ifdef CONFIG_MOBILEVISOR - spl_phase_trace(PHASE_CHECK_SEC_SYSDUMP); - sysdump_mode = bootmode_check_sysdump(); - if (!sysdump_mode) { - ddr_print_string("\r\nStart load vmm images from emmc\r\n"); - /* reserve KEY_INFO_SIZE for image loading area */ - ret = load_partition_with_header("secvm", CONFIG_SECVM_SIZE - KEY_INFO_SIZ, - (uint8*)CONFIG_SECVM_ADDR, - (sys_img_header*)(CONFIG_SECVM_ADDR - KEY_INFO_SIZ)); - if (ret < 0){ - ddr_print_string("load secvm fail\r\n"); - spl_error_handler(PHASE_LOAD_VMM_IMG_FAILED); - } - ret = load_partition_with_header("mvconfig", CONFIG_MVCONFIG_SIZE - KEY_INFO_SIZ, - (uint8*)CONFIG_MVCONFIG_ADDR, - (sys_img_header*)(CONFIG_MVCONFIG_ADDR - KEY_INFO_SIZ)); - if (ret < 0){ - ddr_print_string("load mvconfig fail\r\n"); - spl_error_handler(PHASE_LOAD_VMM_IMG_FAILED); - } - ret = load_partition_with_header("mobilevisor", CONFIG_MOBILEVISOR_SIZE - KEY_INFO_SIZ, - (uint8*)CONFIG_MOBILEVISOR_ADDR, - (sys_img_header*)(CONFIG_MOBILEVISOR_ADDR - KEY_INFO_SIZ)); - if (ret < 0){ - ddr_print_string("load mobilevisor fail\r\n"); - spl_error_handler(PHASE_LOAD_VMM_IMG_FAILED); - } - ddr_print_string("Load vmm images succ\r\n"); - } -#endif + load_partition_with_header(uboot_part[PART_INDEX + i],CONFIG_UBOOT_MAX_SIZE, + CONFIG_SYS_NAND_U_BOOT_DST,(sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - KEY_INFO_SIZ)); + #ifdef CONFIG_DUAL_SPL//only for tshark3 dual spl; if(Spl_Hash_Exist(uboot_start_hash_addr+UBOOT_HASH_SIZE_OFFSET,HASH_TEMP_LEN)) { if(0!=Hash_Check()) { - load_partition_with_header("uboot_bak",CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST,(sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - EMMC_SECTOR_SIZE)); + load_partition_with_header("uboot_bak",CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST, + (sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - EMMC_SECTOR_SIZE)); if(0!=Hash_Check()) { spl_error_handler(PHASE_BOOTLOADER_HASH_CHECK_FAILED); } @@ -882,14 +815,16 @@ void nand_boot(void) /*no sec boot ,dual-backup*/ #ifdef CONFIG_SMLBOOT if(0 != sprd_hash_check((uint8_t*)(sml_ldaddr_start-IMAGE_HEAD_SIZE))){ - load_partition_with_header("sml_bak", SML_LOAD_MAX_SIZE,sml_ldaddr_start,(sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); + load_partition_with_header("sml_bak", SML_LOAD_MAX_SIZE,sml_ldaddr_start, + (sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); if(0 != sprd_hash_check((uint8_t*)(sml_ldaddr_start-IMAGE_HEAD_SIZE))) { spl_error_handler(PHASE_SML_HASH_CHECK_FAILED);//sml hash check fail } } if(0 != sprd_hash_check((uint8_t*)(tos_ldaddr_start-IMAGE_HEAD_SIZE))){ - load_trustos_with_header("trustos_bak", TOS_LOAD_MAX_SIZE,tos_ldaddr_start,(sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); + load_trustos_with_header("trustos_bak", TOS_LOAD_MAX_SIZE,tos_ldaddr_start, + (sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); if(0 != sprd_hash_check((uint8_t*)(tos_ldaddr_start-IMAGE_HEAD_SIZE))) { spl_error_handler(PHASE_TOS_HASH_CHECK_FAILED);//tos hash check fail } @@ -898,7 +833,8 @@ void nand_boot(void) #endif if(0 != sprd_hash_check((uint8_t*)(CONFIG_SYS_NAND_U_BOOT_DST-IMAGE_HEAD_SIZE))){ - load_partition_with_header("uboot_bak",CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST,(sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - EMMC_SECTOR_SIZE)); + load_partition_with_header("uboot_bak",CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST, + (sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - EMMC_SECTOR_SIZE)); if(0 != sprd_hash_check((uint8_t*)(CONFIG_SYS_NAND_U_BOOT_DST-IMAGE_HEAD_SIZE))){ #ifdef CONFIG_SD_BOOT if (TRUE == SD_Init()) { @@ -908,20 +844,6 @@ void nand_boot(void) spl_error_handler(PHASE_BOOTLOADER_HASH_CHECK_FAILED); } } -#ifdef CONFIG_MOBILEVISOR -/*we now check hash of vmm image*/ - if (!sysdump_mode) { - if(0 != sprd_hash_check((uint8_t*)(CONFIG_SECVM_ADDR-IMAGE_HEAD_SIZE))){ - spl_error_handler(PHASE_VMM_HASH_CHECK_FAILED); - } - if(0 != sprd_hash_check((uint8_t*)(CONFIG_MVCONFIG_ADDR-IMAGE_HEAD_SIZE))){ - spl_error_handler(PHASE_VMM_HASH_CHECK_FAILED); - } - if(0 != sprd_hash_check((uint8_t*)(CONFIG_MOBILEVISOR_ADDR-IMAGE_HEAD_SIZE))){ - spl_error_handler(PHASE_VMM_HASH_CHECK_FAILED); - } - } -#endif #endif #endif @@ -950,7 +872,8 @@ void nand_boot(void) #else #if !defined(AB_PARTITIONS) && !defined(CONFIG_ANDROID_AB) /***secboot sml dual_backup***/ - load_partition_with_header("sml_bak", SML_LOAD_MAX_SIZE,sml_ldaddr_start,(sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); + load_partition_with_header("sml_bak", SML_LOAD_MAX_SIZE,sml_ldaddr_start, + (sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(sml_ldaddr_start-IMAGE_HEAD_SIZE),NULL,NULL,SECURE_BOOT))) { spl_error_handler(PHASE_SML_SV_FAILED); @@ -971,7 +894,8 @@ void nand_boot(void) #else #if !defined(AB_PARTITIONS) && !defined(CONFIG_ANDROID_AB) /***secboot tos dual_backup***/ - load_trustos_with_header("trustos_bak", TOS_LOAD_MAX_SIZE,tos_ldaddr_start,(sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); + load_trustos_with_header("trustos_bak", TOS_LOAD_MAX_SIZE,tos_ldaddr_start, + (sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(tos_ldaddr_start-IMAGE_HEAD_SIZE),"trustos",NULL,SECURE_BOOT))) { spl_error_handler(PHASE_TOS_SV_FAILED); @@ -982,24 +906,6 @@ void nand_boot(void) #endif } -#ifdef CONFIG_MOBILEVISOR - if (!sysdump_mode) { - if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(CONFIG_SECVM_ADDR - KEY_INFO_SIZ),NULL,NULL,SECURE_BOOT))) - { - spl_error_handler(PHASE_VMM_SV_FAILED); - } - - if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(CONFIG_MVCONFIG_ADDR - KEY_INFO_SIZ),NULL,NULL,SECURE_BOOT))) - { - spl_error_handler(PHASE_VMM_SV_FAILED); - } - - if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(CONFIG_MOBILEVISOR_ADDR - KEY_INFO_SIZ),NULL,NULL,SECURE_BOOT))) - { - spl_error_handler(PHASE_VMM_SV_FAILED); - } - } -#endif spl_phase_trace(PHASE_VERIFY_BOOTLOADER); if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(CONFIG_SYS_NAND_U_BOOT_DST - SECURE_HEADER_OFF),NULL,NULL,SECURE_BOOT))) { @@ -1010,7 +916,8 @@ void nand_boot(void) #else #if !defined(AB_PARTITIONS) && !defined(CONFIG_ANDROID_AB) /***secboot uboot dual_backup***/ - load_partition_with_header("uboot_bak",CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST,(sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - EMMC_SECTOR_SIZE)); + load_partition_with_header("uboot_bak",CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST, + (sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - EMMC_SECTOR_SIZE)); if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(CONFIG_SYS_NAND_U_BOOT_DST - SECURE_HEADER_OFF),NULL,NULL,SECURE_BOOT))) { @@ -1043,17 +950,9 @@ if (!sysdump_mode) } else { uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; } -#else -#ifdef CONFIG_MOBILEVISOR - if (sysdump_mode) { - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; - } else { - uboot = (void *)CONFIG_MOBILEVISOR_ADDR; - } #else uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; #endif -#endif #ifdef CONFIG_SECURE_BOOT #if defined(CONFIG_SC8830) || defined(CONFIG_SC9630) || defined(CONFIG_SCX35L64) diff --git a/nand_spl/sd_boot.c b/nand_spl/sd_boot.c index f20c825ca..873d206cb 100755 --- a/nand_spl/sd_boot.c +++ b/nand_spl/sd_boot.c @@ -17,14 +17,15 @@ #include #include #include +#include #ifdef CONFIG_CHIP_ENV_SET #include #endif +#include #include #include #include #include -#include #include #include #include @@ -33,6 +34,8 @@ #include #include #endif +#include + #define SECURE_HEADER_OFF 512 @@ -64,6 +67,122 @@ int8_t sprd_hash_check(uint8_t *header) #endif #endif +extern void dmc_print_str(const char *string); +#ifdef CONFIG_DEBUG_LOG +#define debugf(x) dmc_print_str(x) +#else +#define debugf(x) +#endif + +#define BOOT_FLAG_SLOT_A (0xA5) +#define BOOT_FLAG_SLOT_B (0x0) + +extern slot_enum_t slot_ab; + +#ifdef CONFIG_SPL_DOUBLE_SLOT +uint8_t dual_spl_enable(void) +{ + uint32 dual_spl = 0; + Efuse_Result_Ret ret; + + ret = efuse_read_drv(EFUSE_DUAL_SPL_ENABLE_INDEX, EFUSE_DUAL_SPL_ENABLE_INDEX, &dual_spl, 1); + if (ret != EFUSE_RESULT_SUCCESS) { + dmc_print_str("efuse read error\n"); + return 0; + } + if (dual_spl & EFUSE_DUAL_SPL_ENABLE_BIT) + return 1; + else + return 0; +} + +uint8_t adjust_slot_ab(void) +{ + uint32 BootSlot = 0; + + BootSlot = SPL_GetBootSlot(); + if ((slot_ab == SLOT_A && BootSlot == BOOT_FLAG_SLOT_A) || (slot_ab == SLOT_B && BootSlot == BOOT_FLAG_SLOT_B)) + return 1; + else + return 0; +} +#endif + +#ifdef CONFIG_EXIT_FUN +extern int do_board_func(void); +#endif + +#ifdef CONFIG_SCX35L64 +extern void switch64_and_set_pc(u32 addr); +#endif + + +#ifdef CONFIG_DUAL_SPL +/* these parameter used to get the size of uboot.bin from sec header*/ +#define SEHEADER_UBOOT_SIZE_OFFSET 0x30 +#define BYTE3 0x03 +#define BYTE2 0x02 +#define BYTE1 0x01 +#define BYTE0 0x0 +uint8 hash_temp[HASH_TEMP_LEN]={0}; +unsigned long uboot_size_no_hash=0; +uint8 *uboot_start_addr = CONFIG_SYS_NAND_U_BOOT_DST;//0x9f00_0000 +uint8 *uboot_start_hash_addr = CONFIG_SYS_NAND_U_BOOT_DST-EMMC_SECTOR_SIZE; +uint8 *uboot_size_no_hash_addr=CONFIG_SYS_NAND_U_BOOT_DST-EMMC_SECTOR_SIZE+SEHEADER_UBOOT_SIZE_OFFSET; +BOOLEAN Spl_Hash_Exist(uint8 *p_hash,uint hash_len) +{ + uint32 i; + for(i=0;i= retrys) - return -1; - image_size = pHeader->mImgSize; - #ifdef CONFIG_SECBOOT - image_size = image_size + SECBOOT_CERTIFICATE_SIZE; /*secure cert size*/ - #endif - if (image_size > img_max_size) { - return -2; - } - - /* read image */ - for(i = 0; i < retrys; i++){ - if(0==read_common_partition(dev, partition, KEY_INFO_SIZ/dev->blksz, - image_size, img_buf)) - break; - } - if(i >= retrys) - return -3; - - return 0; +int load_common_partition(uchar * partition_name,uint32_t size, uint8_t* buf) +{ + int i, retrys = 5; + block_dev_desc_t *dev = NULL; + dev = get_dev(); + + if (NULL == dev) + return -1; + + for(i =0; i= retrys) + return -1; + image_size = pHeader->mImgSize; + #ifdef CONFIG_SECBOOT + image_size = image_size + SECBOOT_CERTIFICATE_SIZE; /*secure cert size*/ + #endif + if (image_size > img_max_size) { + return -2; + } + + /* read image */ + for(i = 0; i < retrys; i++){ + if(0==read_common_partition(dev, partition, KEY_INFO_SIZ/dev->blksz, + image_size, img_buf)) + break; + } + if(i >= retrys) + return -3; + + return 0; +} + +#ifdef CONFIG_SUPPORT_FLASH_WRITE +int write_common_partition(uchar * partition_name,uint32_t size, uint32_t offset, uint8_t* buf) +{ + block_dev_desc_t *dev = NULL; + uint32_t offb, start, blk_cnt, header_sz; + disk_partition_t info; + unsigned char temp[EMMC_SECTOR_SIZE]; + + dev = get_dev(); + + if (NULL == dev || NULL == buf || dev->blksz != EMMC_SECTOR_SIZE) + return -1; + + if (get_partition_info_by_name(dev, partition_name, &info)) + return -1; + + start = offset / EMMC_SECTOR_SIZE; + offb = offset % EMMC_SECTOR_SIZE; + + if(start > info.size || (offset + size - 1)/ EMMC_SECTOR_SIZE > info.size) + return -1; + + start += info.start; + + if (0 != offb) { + header_sz = EMMC_SECTOR_SIZE - offb; + if (FALSE == dev->block_read(dev->dev, start, 1, temp)) { + return -1; + } + if (size <= header_sz) { + sprd_memcpy(temp + offb, buf, size); + size = 0; + } else { + sprd_memcpy(temp + offb, buf, header_sz); + buf += header_sz; + size -= header_sz; + } + + if (FALSE == dev->block_write(dev->dev, start, 1, temp)) { + return -1; + } + start++; + } + + blk_cnt = size / EMMC_SECTOR_SIZE; + + if (blk_cnt > 0) { + if (FALSE == dev->block_write(dev->dev, start, blk_cnt, buf)) { + return -1; + } + start += blk_cnt; + buf += ((uint64_t)blk_cnt * EMMC_SECTOR_SIZE); + size = size % EMMC_SECTOR_SIZE; + } + + if (size > 0) { + if (FALSE == dev->block_read(dev->dev, start, 1, temp)) { + return -1; + } + sprd_memcpy(temp, buf, size); + if (FALSE == dev->block_write(dev->dev, start, 1, temp)) { + return -1; + } + } + + return 0; +} +#else +int write_common_partition(uchar * partition_name,uint32_t size, uint32_t offset,uint8_t* buf) +{ + return -1; +} +#endif + +#ifdef CONFIG_DUAL_SPL +int Hash_Check(void)///add the hash_check +{ + uboot_size_no_hash=((*(uboot_size_no_hash_addr+BYTE3))<<24)|((*(uboot_size_no_hash_addr+BYTE2))<<16)| + ((*(uboot_size_no_hash_addr+BYTE1))<<8)|(*(uboot_size_no_hash_addr+BYTE0)); + sha256_csum_wd(uboot_start_addr,uboot_size_no_hash,hash_temp,NULL); + if(0==sprd_memcmp(uboot_start_hash_addr+UBOOT_HASH_SIZE_OFFSET,hash_temp,HASH_TEMP_LEN)) + return 0; + else + return -1; +} +#endif//end hash_check + +/*whale2 and new project,dual backup function will this interface*/ +#ifdef CONFIG_DUAL_BACKUP +/*secboot mode ,no need use this interface*/ +#ifndef CONFIG_SECBOOT +BOOLEAN sprd_hash_exist(uint8 *p_hash,uint hash_len) +{ + uint32 i; + for(i=0;imPayloadHash,32)){//exsit hash + sha256_csum_wd((uint8_t *)(header+sizeof(sys_img_header)),img_header->mImgSize,hash_temp,NULL); + if(0 == sprd_memcmp(img_header->mPayloadHash,hash_temp,32)) + return 0; + else + return -1; + } + return 0;//no need to check hash +} +#endif +#endif + +#if defined(CONFIG_WHALE) || defined(CONFIG_WHALE2) +#define TMP_REG_AP_AHB_AHB_EB 0x20210000 +#define TMP_BIT_AP_AHB_CC63P_EB (1<<23) +void disable_ahb_cc63_eb() +{ + (*(volatile uint32 *)TMP_REG_AP_AHB_AHB_EB) &= (uint32)(~TMP_BIT_AP_AHB_CC63P_EB); +} +#endif + +#define HWRST_POWERON_MASK (0xf0) + /* - * The main entry for NAND booting. It's necessary that SDRAM is already - * configured and available since this code loads the main U-Boot image - * from NAND into SDRAM and starts it from there. - */ +* Definition of ANA_RST_STATUS(ANA_REG_GLB_POR_RST_MONITOR) register +* bit[0..7]: Reboot mode +* bit[9]: SYSDUMP enable/disable flag +*/ + +#define HWRST_STATUS_BOOTLOADER_PANIC (0x0010) +#define HWRST_STATUS_RECOVERY (0x0020) +#define HWRST_STATUS_FASTBOOT (0x0030) +#define HWRST_STATUS_NORMAL (0x0040) +#define HWRST_STATUS_ALARM (0x0050) +#define HWRST_STATUS_SLEEP (0x0060) +#define HWRST_STATUS_SPECIAL (0x0070) +#define HWRST_STATUS_CALIBRATION (0x0090) +#define HWRST_STATUS_PANIC (0x0080) +#define HWRST_STATUS_AUTODLOADER (0x00a0) +#define HWRST_STATUS_IQMODE (0x00b0) +#define HWRST_STATUS_SPRDISK (0x00c0) +#define HWRST_STATUS_SILENT (0x00d0) +#define HWRST_STATUS_NORMAL2 (0x00f0) +#define HWRST_STATUS_NORMAL3 (0x00f1) +#define HWRST_STATUS_SYSDUMPEN (0x0200) +#define HWRST_MOBILEVISOR (0x0001) +#define HWRST_STATUS_TOS_PANIC (0x0002) +#define HWRST_STATUS_SML_PANIC (0x0004) + +int8_t check_sprd_sysdump_sec() +{ + uint32 reg_rst_moitor = 0; + + //read sc2731 RST_MONITOR reg, 0x2E8 + reg_rst_moitor = ANA_REG_GET(ANA_REG_GLB_POR_RST_MONITOR); + + reg_rst_moitor &= 0xFF; + + //return status by HWRST + if ((reg_rst_moitor == HWRST_STATUS_TOS_PANIC) || (reg_rst_moitor == HWRST_STATUS_SML_PANIC)) { + return 1; + } else { + return 0; + } +} + +#define PART_INDEX 0 +#if defined(AB_PARTITIONS) || defined(CONFIG_ANDROID_AB) +static const char tos_part[][16] = { + "trustos_a", + "trustos_b" +}; + +static const char teecfg_part[][16] = { + "teecfg_a", + "teecfg_b" +}; + +static const char sml_part[][16] = { + "sml_a", + "sml_b" +}; + +static const char uboot_part[][16] = { + "uboot_a", + "uboot_b" +}; +#else +static const char tos_part[][16] = { + "trustos", + "trustos_bak" +}; + +static const char teecfg_part[][16] = { + "teecfg", + "teecfg_bak" +}; + +static const char sml_part[][16] = { + "sml", + "sml_bak" +}; + +static const char uboot_part[][16] = { + "uboot", + "uboot_bak" +}; +#endif + +#ifdef AB_PARTITIONS +int select_ab(uint8_t *successful_flag) +{ + int ret, slot, i; + int current = 0; + char *line, *next; + + struct uboot_env_redund *buf[2]; + uint32_t vendor_space_offset_in_misc = 1024; + ret = load_common_partition("misc", vendor_space_offset_in_misc, (char *)CONFIG_SYS_NAND_U_BOOT_DST); + if (ret) { + dmc_print_str("laod misc partiton fail!\n"); + return 0; + } + + buf[0] = (struct uboot_env_redund *)(CONFIG_SYS_NAND_U_BOOT_DST); + + ret = load_common_partition("misc_bak", vendor_space_offset_in_misc, + (char *)(CONFIG_SYS_NAND_U_BOOT_DST + vendor_space_offset_in_misc + 1)); + if (ret) { + dmc_print_str("laod misc_bak partiton fail!\n"); + return 0; + } + + buf[1] = (struct uboot_env_redund *)(CONFIG_SYS_NAND_U_BOOT_DST + vendor_space_offset_in_misc + 1); + + if (buf[1]->flags > buf[0]->flags) + current = 1; + else + current = 0; + + if (buf[0]->flags == 0xFF && buf[1]->flags == 0) + current = 1; + else if (buf[1]->flags == 0xFF && buf[0]->flags == 0) + current = 0; + + char *temp = buf[current]->data; + + for (line = temp; *line; line = next + 1) { + char *value; + + /* + * Search the end of the string pointed by line + */ + for (next = line; *next; ++next) { + if ((next - (char *)temp) > vendor_space_offset_in_misc) { + return 0; + } + } + + value = strchr(line, '='); + if (!value) + continue; + + *value++ = '\0'; + + for (i = 0; i < KEY_MAX; i++) { + if (sprd_strcmp(line, misc_key_str[i]) == 0) { + misc_data[i] = value; + } + } + } + + if (!sprd_strcmp(misc_data[KEY_DOUBLE_COPY], "y")) { + char startota= misc_data[KEY_STARTOTA]; + switch(startota) { + case '0': + case '1': + if (misc_data[KEY_CURRENT_MODE] == 'b') + ret = 1; + else + ret = 0; + break; + case '2': + if (misc_data[KEY_RETRY_MODE] == 'a') + ret = 0; + else if (misc_data[KEY_RETRY_MODE] == 'b') + ret = 1; + else + ret = misc_data[KEY_CURRENT_MODE] - 'a'; + *successful_flag = 1; + break; + default: + dmc_print_str("select_ab: startota use default in misc partition!!!\n"); + ret = 0; + break; + } + }else { + dmc_print_str("select_ab double_copy in misc partition!!!\n"); + ret = 0; + } + + return ret; +} +#endif + +#ifdef CONFIG_ANDROID_AB +extern int select_ab(uint8_t *successful_flag); +extern int check_spl_destoried(void); + +static void jump_to_uboot(int i) +{ + __attribute__ ((noreturn)) void (*uboot) (unsigned long, unsigned long); + + load_partition_with_header(uboot_part[PART_INDEX + i],CONFIG_UBOOT_MAX_SIZE, + CONFIG_SYS_NAND_U_BOOT_DST,(sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - KEY_INFO_SIZ)); + chipram_env_set(BOOTLOADER_MODE_LOAD); + spl_phase_trace(PHASE_JUMP_TO_BOOTLOADER); + spl_save_trace_flag(); +#ifdef CONFIG_SWITCH_FUN + do_secure_state_switch(); +#endif + +#ifdef CONFIG_EXIT_FUN + do_board_func(); +#endif + +#ifdef CONFIG_SCX35L64 + switch64_and_set_pc(CONFIG_SYS_NAND_U_BOOT_START); +#endif + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + (*uboot)(0,0); +} + +void adjust_spl(int i, uint8_t dual_spl) +{ + chipram_env_t *env; + uint8_t do_adjust = 0; + uint8_t spl_status = 0; + + env = (struct chipram_env *)CHIPRAM_ENV_ADDR; +#ifdef CONFIG_SPL_DOUBLE_SLOT + dual_spl = dual_spl_enable(); + if (dual_spl) { + env->dual_spl_flag = 0x1; + if (!adjust_slot_ab()) { + dmc_print_str("adjust slot fail\n"); + env->spl_edit_flag = 0x1; + do_adjust = 1; + } else { + env->spl_edit_flag = 0x0; + dmc_print_str("adjust slot success\n"); + return; + } + } else { + env->dual_spl_flag = 0x0; + env->spl_edit_flag = 0x0; + } +#endif + spl_status = check_spl_destoried(); + if (spl_status != 0 && do_adjust == 0) { + /*main spl can not loaded here*/ + if (spl_status == 1)/*to repair SPL*/ + env->spl_adjust_flag = 0x55CC55CC; + else if (spl_status == 2)/*to destory SPL*/ + env->spl_adjust_flag = 0x55DD55DD; + do_adjust = 1; + } + + if(do_adjust){ + dmc_print_str("\r\n adjust spl\n"); + jump_to_uboot(i); + } +} +#endif + void nand_boot(void) { int ret; + int i = 0; +#if defined(AB_PARTITIONS) || defined(CONFIG_ANDROID_AB) + uint8_t successful = 0; + uint8_t dual_spl = 0; +#endif __attribute__((noreturn)) void (*uboot)(unsigned long, unsigned long); + int8_t sysdump_mode = 0, sysdump_security = 0; uint64_t sml_ldaddr_start = 0; uint64_t tos_ldaddr_start = 0; - - /* - * Init board specific nand support - */ + int tos_aslr_seed = 0; +#ifdef CONFIG_TOS_ASLR_SEED + uint8_t rng[4]; + sprd_rng_gen(rng, 4); + tos_aslr_seed = *(int*)rng; +#endif #ifdef CONFIG_SML_LDADDR_START sml_ldaddr_start = CONFIG_SML_LDADDR_START; #endif #ifdef CONFIG_TOS_LDADDR_START tos_ldaddr_start = CONFIG_TOS_LDADDR_START; #endif +#ifdef CONFIG_TEECFG_CUSTOM + sprd_fw_attr fw_attr; + fw_attr.teecfg_addr = CONFIG_TEECFG_LDADDR_START; + fw_attr.teecfg_size = CONFIG_TEECFG_MEM_SIZE; +#endif + + //Init board specific nand support + spl_phase_trace(PHASE_ENTER_NAND_BOOT); - sprd_firewall_config_pre(); + spl_phase_trace(PHASE_CHECK_SEC_SYSDUMP); + sysdump_security = check_sprd_sysdump_sec(); + if (!sysdump_security) { //sysdump mode (tos panic) don't enable firewall + sprd_firewall_config_pre(); + } + spl_phase_trace(PHASE_FLASH_INIT); ret = SD_Init(); BUG_ON(!ret); +#if defined(AB_PARTITIONS) || defined(CONFIG_ANDROID_AB) + spl_phase_trace(PHASE_SELECT_AB); + i = select_ab(&successful); + if (i < 0) { + spl_error_handler(PHASE_SELECT_AB_FAILED); + } +#ifdef CONFIG_ANDROID_AB + adjust_spl(i, dual_spl); +#endif +#endif + +#if CONFIG_SMLBOOT// whale + load_partition_with_header(sml_part[PART_INDEX + i], SML_LOAD_MAX_SIZE, + sml_ldaddr_start,(sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); + load_trustos_with_header(tos_part[PART_INDEX + i], TOS_LOAD_MAX_SIZE, + tos_ldaddr_start,(sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); +#endif /* * Load U-Boot image from NAND into RAM */ + if (!sysdump_security) { //sysdump mode (tos panic) don't load tos and sml +#ifdef CONFIG_TEECFG_CUSTOM + spl_phase_trace(PHASE_LOAD_TEE_IMG); + ret = load_partition_with_header("teecfg", TEECFG_LOAD_MAX_SIZE,CONFIG_TEECFG_LDADDR_START, + (sys_img_header*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE)); + BUG_ON(ret); + + +#ifdef CONFIG_SECBOOT + if (SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN, (CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE), NULL, NULL, SECURE_BOOT))) { +#if !defined(CONFIG_DUAL_BACKUP) +#if defined(AB_PARTITIONS) || defined(CONFIG_ANDROID_AB) + spl_error_handler(PHASE_TEE_SV_FAILED); +#endif + +#else +#if !defined(AB_PARTITIONS) && !defined(CONFIG_ANDROID_AB) + /***secboot teecfg dual_backup***/ + load_partition_with_header("teecfg_bak", TEECFG_LOAD_MAX_SIZE, CONFIG_TEECFG_LDADDR_START, + (sys_img_header*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE)); + if (SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN, (CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE), NULL, NULL, SECURE_BOOT))) { + spl_error_handler(PHASE_TEE_SV_FAILED); + } +#endif + +#endif + } +#else +#if defined(CONFIG_DUAL_BACKUP) && defined(CONFIG_SMLBOOT) + if (0 != sprd_hash_check((uint8_t*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE))) { + load_partition_with_header("teecfg_bak", TEECFG_LOAD_MAX_SIZE, CONFIG_TEECFG_LDADDR_START, + (sys_img_header*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE)); + if (0 != sprd_hash_check((uint8_t*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE))) { + spl_error_handler(PHASE_TEE_HASH_CHECK_FAILED); + } + } +#endif +#endif + + + spl_phase_trace(PHASE_GET_TOS_SML_ADDR); + if (teecfg_get_reserved_val("tee_sml_addr", &sml_ldaddr_start) < 0 || \ + teecfg_get_reserved_val("tee_tos_addr", &tos_ldaddr_start) < 0) { + dmc_print_str("get sml/tos addr error!\n"); + spl_error_handler(PHASE_GET_TOS_SML_ADDR_FAILED); + } else { + fw_attr.sml_addr = sml_ldaddr_start; + fw_attr.tos_addr = tos_ldaddr_start; + } +#endif #ifdef CONFIG_LOAD_ATF - ret = load_partition_with_header("sml", SML_LOAD_MAX_SIZE,sml_ldaddr_start,(sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); + ret = load_partition_with_header("sml", SML_LOAD_MAX_SIZE, + sml_ldaddr_start,(sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); BUG_ON(ret); #endif #ifdef CONFIG_LOAD_TOS_ALONE - ret = load_trustos_with_header("trustos", TOS_LOAD_MAX_SIZE,tos_ldaddr_start,(sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); + ret = load_trustos_with_header("trustos", TOS_LOAD_MAX_SIZE, + tos_ldaddr_start,(sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); BUG_ON(ret); #endif + } -#ifdef CONFIG_TEECFG_CUSTOM - load_partition_with_header("teecfg", TEECFG_LOAD_MAX_SIZE, CONFIG_TEECFG_LDADDR_START, (sys_img_header*)(CONFIG_TEECFG_LDADDR_START - IMAGE_HEAD_SIZE)); + spl_phase_trace(PHASE_LOAD_BOOTLOADER); + ret = load_partition_with_header("uboot", CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST, + (sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - KEY_INFO_SIZ)); BUG_ON(ret); + +#ifdef CONFIG_DUAL_SPL//only for tshark3 dual spl; + if(Spl_Hash_Exist(uboot_start_hash_addr+UBOOT_HASH_SIZE_OFFSET,HASH_TEMP_LEN)) + { + if(0!=Hash_Check()) { + load_partition_with_header("uboot_bak",CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST, + (sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - EMMC_SECTOR_SIZE)); + if(0!=Hash_Check()) { + spl_error_handler(PHASE_BOOTLOADER_HASH_CHECK_FAILED); + } + } + } #endif - ret = load_partition_with_header("uboot", CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST,(sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - KEY_INFO_SIZ)); - BUG_ON(ret); +#ifdef CONFIG_DUAL_BACKUP +#ifdef CONFIG_SECBOOT + /*sec boot ,dual-backup*/ +#else + /*no sec boot ,dual-backup*/ +#ifdef CONFIG_SMLBOOT + if(0 != sprd_hash_check((uint8_t*)(sml_ldaddr_start-IMAGE_HEAD_SIZE))){ + load_partition_with_header("sml_bak", SML_LOAD_MAX_SIZE,sml_ldaddr_start, + (sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); + if(0 != sprd_hash_check((uint8_t*)(sml_ldaddr_start-IMAGE_HEAD_SIZE))) { + spl_error_handler(PHASE_SML_HASH_CHECK_FAILED);//sml hash check fail + } + } + + if(0 != sprd_hash_check((uint8_t*)(tos_ldaddr_start-IMAGE_HEAD_SIZE))){ + load_trustos_with_header("trustos_bak", TOS_LOAD_MAX_SIZE,tos_ldaddr_start, + (sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); + if(0 != sprd_hash_check((uint8_t*)(tos_ldaddr_start-IMAGE_HEAD_SIZE))) { + spl_error_handler(PHASE_TOS_HASH_CHECK_FAILED);//tos hash check fail + } + } +#endif + + if(0 != sprd_hash_check((uint8_t*)(CONFIG_SYS_NAND_U_BOOT_DST-IMAGE_HEAD_SIZE))){ + load_partition_with_header("uboot_bak",CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST, + (sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - EMMC_SECTOR_SIZE)); + if(0 != sprd_hash_check((uint8_t*)(CONFIG_SYS_NAND_U_BOOT_DST-IMAGE_HEAD_SIZE))){ + spl_error_handler(PHASE_BOOTLOADER_HASH_CHECK_FAILED); + } + } +#endif +#endif + + +#ifdef CONFIG_SECBOOT + spl_phase_trace(PHASE_GET_TOS_SML_SIZE); + if (!sysdump_security) { //sysdump mode (tos panic) don't verify tos and sml +#ifdef CONFIG_TEECFG_CUSTOM + if (teecfg_get_reserved_val("tee_sml_size", &(fw_attr.sml_size)) < 0 || \ + teecfg_get_reserved_val("tee_tos_size", &(fw_attr.tos_size)) < 0) { + dmc_print_str("get sml/tos size error!\n"); + spl_error_handler(PHASE_GET_SML_TOS_SIZE_FAILED); + } + sprd_firewall_config_attr(&fw_attr); +#endif + +#if defined(CONFIG_SMLBOOT)|| defined(CONFIG_LOAD_ATF) + spl_phase_trace(PHASE_VERIFY_SML); + if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(sml_ldaddr_start-IMAGE_HEAD_SIZE),NULL,NULL,SECURE_BOOT))) + { + +#if !defined(CONFIG_DUAL_BACKUP) +#if defined(AB_PARTITIONS) || defined(CONFIG_ANDROID_AB) + spl_error_handler(PHASE_SML_SV_FAILED); +#endif + +#else + +#if !defined(AB_PARTITIONS) && !defined(CONFIG_ANDROID_AB) + /***secboot sml dual_backup***/ + load_partition_with_header("sml_bak", SML_LOAD_MAX_SIZE,sml_ldaddr_start, + (sys_img_header*)(sml_ldaddr_start-IMAGE_HEAD_SIZE)); + if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(sml_ldaddr_start-IMAGE_HEAD_SIZE),NULL,NULL,SECURE_BOOT))) + { + spl_error_handler(PHASE_SML_SV_FAILED); + } +#endif + +#endif + } +#endif + +#if defined(CONFIG_SMLBOOT)|| defined(CONFIG_LOAD_TOS_ALONE) + spl_phase_trace(PHASE_VERIFY_TOS); + if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(tos_ldaddr_start-IMAGE_HEAD_SIZE),"trustos",NULL,SECURE_BOOT))) + { +#if !defined(CONFIG_DUAL_BACKUP) +#if defined(AB_PARTITIONS) || defined(CONFIG_ANDROID_AB) + spl_error_handler(PHASE_TOS_SV_FAILED); +#endif +#else + +#if !defined(AB_PARTITIONS) && !defined(CONFIG_ANDROID_AB) + /***secboot tos dual_backup***/ + load_trustos_with_header("trustos_bak", TOS_LOAD_MAX_SIZE,tos_ldaddr_start, + (sys_img_header*)(tos_ldaddr_start-IMAGE_HEAD_SIZE)); + if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(tos_ldaddr_start-IMAGE_HEAD_SIZE),"trustos",NULL,SECURE_BOOT))) + { + spl_error_handler(PHASE_TOS_SV_FAILED); + } +#endif + +#endif + } +#endif + } + + spl_phase_trace(PHASE_VERIFY_BOOTLOADER); + if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(CONFIG_SYS_NAND_U_BOOT_DST - SECURE_HEADER_OFF),NULL,NULL,SECURE_BOOT))) + { + +#if !defined(CONFIG_DUAL_BACKUP) +#if defined(AB_PARTITIONS) || defined(CONFIG_ANDROID_AB) + spl_error_handler(PHASE_BOOTLOADER_SV_FAILED); +#endif +#else + +#if !defined(AB_PARTITIONS) && !defined(CONFIG_ANDROID_AB) + /***secboot uboot dual_backup***/ + load_partition_with_header("uboot_bak",CONFIG_UBOOT_MAX_SIZE,CONFIG_SYS_NAND_U_BOOT_DST, + (sys_img_header*)(CONFIG_SYS_NAND_U_BOOT_DST - EMMC_SECTOR_SIZE)); + if(SECBOOT_VERIFY_SUCCESS != (secboot_verify(IRAM_BEGIN,(CONFIG_SYS_NAND_U_BOOT_DST - SECURE_HEADER_OFF),NULL,NULL,SECURE_BOOT))) + { + spl_error_handler(PHASE_BOOTLOADER_SV_FAILED); + } +#endif + +#endif + } + +#if defined(AB_PARTITIONS) || defined(CONFIG_ANDROID_AB) +if ((!sysdump_mode)&&(successful || dual_spl)) + update_swVersion(); +#else +if (!sysdump_mode) + update_swVersion(); +#endif + +#endif /* * Jump to U-Boot image */ #if CONFIG_SMLBOOT || CONFIG_LOAD_ATF - uboot = (void *)CONFIG_SML_LDADDR_START; + if (!sysdump_security) { + uboot = (void *)sml_ldaddr_start; + } else { + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + } #else uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; #endif +#ifdef CONFIG_SECURE_BOOT +#if defined(CONFIG_SC8830) || defined(CONFIG_SC9630) || defined(CONFIG_SCX35L64) + typedef sec_callback_func_t *(*get_secure_checkfunc_t) (sec_callback_func_t *); + sec_callback_func_t sec_callfunc; + vlr_info_t *vlr_info = (vlr_info_t *) (VLR_INFO_OFF); + get_secure_checkfunc_t *get_secure_func = (get_secure_checkfunc_t *) (INTER_RAM_BEGIN + 0x1C); + (*get_secure_func) (&sec_callfunc); + sec_callfunc.secure_check((CONFIG_SYS_NAND_U_BOOT_START - KEY_INFO_SIZ), vlr_info->length, vlr_info, KEY_INFO_OFF); + //sec_callfunc.secure_check((CONFIG_SYS_NAND_U_BOOT_START),vlr_info->length, vlr_info, KEY_INFO_OFF); +#elif defined(CONFIG_FPGA) + +#else + secure_check(CONFIG_SYS_NAND_U_BOOT_START, 0, CONFIG_SYS_NAND_U_BOOT_START + CONFIG_SYS_NAND_U_BOOT_SIZE - VLR_INFO_OFF, + INTER_RAM_BEGIN + CONFIG_SPL_LOAD_LEN - KEY_INFO_SIZ - CUSTOM_DATA_SIZ); +#endif +#endif + + /* disable ahb ccp_en bit */ +#if defined(CONFIG_EFUSE) +#if defined(CONFIG_WHALE) || defined(CONFIG_WHALE2) + sync_efuse_ahb_ccp_eb(); +#endif +#endif + +#if defined(CONFIG_WHALE) || defined(CONFIG_WHALE2) + disable_ahb_cc63_eb(); +#endif disable_ahb_ce_eb(); disable_ahb_ce_efs_eb(); - sprd_firewall_config(); + /***firewall set***/ + if (!sysdump_security) { //sysdump mode (tos panic) don't enable firewall + sprd_firewall_config(); + } +#if defined(CONFIG_CHIP_ENV_SET) chipram_env_set(BOOTLOADER_MODE_LOAD); +#endif + +#ifdef CONFIG_SUPPORT_BOOT_MAINTAIN + write_bootloader_log(); +#endif + spl_phase_trace(PHASE_JUMP_TO_SML); + spl_save_trace_flag(); + +#if (CONFIG_LOAD_TOS_ALONE == 1) && !defined (CONFIG_ATF_BOOT_TOS) + secure_sp_entry(tos_ldaddr_start,CONFIG_SYS_NAND_U_BOOT_START); +#else if(uboot == (void *)CONFIG_SML_LDADDR_START) { #if ((CONFIG_LOAD_TOS_ALONE == 1) && (CONFIG_TEECFG_CUSTOM == 1)) (*uboot)(CONFIG_TOS_LDADDR_START,CONFIG_TEECFG_LDADDR_START); @@ -253,5 +1044,5 @@ void nand_boot(void) } else { (*uboot)(0,0); } - +#endif }